Merge remote-tracking branch 'origin/pr-mk4'

Author: doc-hex

extmod/vfs_fat.c

@@ -379,6 +379,9 @@ STATIC mp_obj_t vfs_fat_mount(mp_obj_t self_in, mp_obj_t readonly, mp_obj_t mkfs
     if (res == FR_NO_FILESYSTEM && mp_obj_is_true(mkfs)) {
         uint8_t working_buf[FF_MAX_SS];
         res = f_mkfs(&self->fatfs, FM_FAT | FM_SFD, 0, working_buf, sizeof(working_buf));
+        if (res == FR_MKFS_ABORTED) { // Probably doesn't support FAT16
+            res = f_mkfs(&self->fatfs, FM_FAT32, 0, working_buf, sizeof(working_buf));
+        }
     }
     if (res != FR_OK) {
         mp_raise_OSError(fresult_to_errno_table[res]);

lib/oofatfs/ffconf.h

@@ -73,7 +73,9 @@
 /* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
 
 
+#ifndef FF_USE_FASTSEEK
 #define FF_USE_FASTSEEK 0
+#endif
 /* This option switches fast seek function. (0:Disable or 1:Enable) */
 
 

lib/stm32lib

@@ -0,0 +1 @@
+../external/micropython

micropython

@@ -1,5 +1,6 @@
 # this file only useful for Coldcard project
 stm32/boards/COLDCARD
+stm32/boards/COLDCARD_MK4
 unix/coldcard-mpy
 unix/unix_random.P
 

ports/.gitignore

@@ -400,6 +400,7 @@ endif
 ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES),f4 f7 h7 l4))
 HAL_SRC_C += $(addprefix $(HAL_DIR)/Src/stm32$(MCU_SERIES)xx_,\
 	hal_sd.c \
+	hal_sd_ex.c \
 	ll_sdmmc.c \
 	ll_fmc.c \
 	)

ports/stm32/Makefile

@@ -29,7 +29,7 @@
 extern const mp_obj_type_t pyb_adc_type;
 extern const mp_obj_type_t pyb_adc_all_type;
 
-#if defined(ADC_CHANNEL_VBAT)
+#if defined(ADC_CHANNEL_VBAT) && MICROPY_HW_ENABLE_ADC
 
 static inline void adc_deselect_vbat(ADC_TypeDef *adc, uint32_t channel) {
     (void)adc;

ports/stm32/adc.h

@@ -351,6 +351,49 @@ static const uint8_t dma_irqn[NSTREAM] = {
     DMA1_Channel4_5_6_7_IRQn,
 };
 
+
+#elif defined(STM32L4) && defined(DMAMUX1)
+
+// newer L4+ series parts have a DMAMUX unit
+#define NCONTROLLERS            (2)
+#define NSTREAMS_PER_CONTROLLER (7)
+#define NSTREAM                 (NCONTROLLERS * NSTREAMS_PER_CONTROLLER)
+
+#define DMA_SUB_INSTANCE_AS_UINT8(dma_request) (dma_request)
+
+#define DMA1_ENABLE_MASK (0x007f) // Bits in dma_enable_mask corresponding to DMA1
+#define DMA2_ENABLE_MASK (0x3f80) // Bits in dma_enable_mask corresponding to DMA2
+
+// DMA1 streams
+const dma_descr_t dma_SPI_1_RX = { DMA1_Channel1, DMA_REQUEST_SPI1_RX, dma_id_0, &dma_init_struct_spi_i2c };
+const dma_descr_t dma_SPI_1_TX = { DMA1_Channel2, DMA_REQUEST_SPI1_TX, dma_id_1, &dma_init_struct_spi_i2c };
+const dma_descr_t dma_SPI_2_RX = { DMA1_Channel3, DMA_REQUEST_SPI2_RX, dma_id_2, &dma_init_struct_spi_i2c };
+const dma_descr_t dma_SPI_2_TX = { DMA1_Channel4, DMA_REQUEST_SPI2_TX, dma_id_3, &dma_init_struct_spi_i2c };
+const dma_descr_t dma_I2C_2_RX = { DMA1_Channel5, DMA_REQUEST_I2C2_RX,  dma_id_4, &dma_init_struct_spi_i2c };
+const dma_descr_t dma_I2C_2_TX = { DMA1_Channel6, DMA_REQUEST_I2C2_TX, dma_id_5, &dma_init_struct_spi_i2c };
+const dma_descr_t dma_I2C_1_RX = { DMA1_Channel5, DMA_REQUEST_I2C1_RX, dma_id_4, &dma_init_struct_spi_i2c };
+const dma_descr_t dma_I2C_1_TX = { DMA1_Channel6, DMA_REQUEST_I2C1_TX, dma_id_5, &dma_init_struct_spi_i2c };
+
+static const uint8_t dma_irqn[NSTREAM] = {
+    DMA1_Channel1_IRQn,
+    DMA1_Channel2_IRQn,
+    DMA1_Channel3_IRQn,
+    DMA1_Channel4_IRQn,
+    DMA1_Channel5_IRQn,
+    DMA1_Channel6_IRQn,
+    DMA1_Channel7_IRQn,
+    DMA2_Channel1_IRQn,
+    DMA2_Channel2_IRQn,
+    DMA2_Channel3_IRQn,
+    DMA2_Channel4_IRQn,
+    DMA2_Channel5_IRQn,
+    DMA2_Channel6_IRQn,
+    DMA2_Channel7_IRQn,
+};
+
+// chip has some special DMA between SDMCC and system
+#undef ENABLE_SDIO
+
 #elif defined(STM32L4)
 
 #define NCONTROLLERS            (2)
@@ -460,6 +503,7 @@ static const uint8_t dma_irqn[NSTREAM] = {
     DMA2_Channel7_IRQn,
 };
 
+
 #elif defined(STM32H7)
 
 #define NCONTROLLERS            (2)
@@ -1044,7 +1088,11 @@ static void dma_idle_handler(uint32_t tick) {
     }
 }
 
-#if defined(STM32F0) || defined(STM32L0) || defined(STM32L4)
+#if defined(STM32L4) && defined(DMAMUX1)
+
+// not required on L4+?
+
+#elif defined(STM32F0) || defined(STM32L0) || defined(STM32L4)
 
 void dma_nohal_init(const dma_descr_t *descr, uint32_t config) {
     DMA_Channel_TypeDef *dma = descr->instance;

ports/stm32/dma.c

@@ -97,6 +97,14 @@ static const flash_layout_t flash_layout[] = {
 };
 #endif
 
+#elif defined(STM32L4S5xx)
+
+// as defined stm32lib/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h
+// - operating in single-bank mode (DBANK=0), total 2M; 8k pages
+static const flash_layout_t flash_layout[] = {
+    { (uint32_t)FLASH_BASE, 0x2000, (2<<20)/0x2000 },
+};
+
 #elif defined(STM32L0) || defined(STM32L4) || defined(STM32WB)
 
 static const flash_layout_t flash_layout[] = {

ports/stm32/flash.c

@@ -113,7 +113,7 @@ STATIC byte flash_cache_mem[0x4000] __attribute__((aligned(4))); // 16k
 #elif defined(STM32L432xx) || \
     defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
     defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L496xx) || \
-    defined(STM32WB)
+    defined(STM32WB) || defined(STM32L4S5xx)
 
 // The STM32L4xx doesn't have CCRAM, so we use SRAM2 for this, although
 // actual location and size is defined by the linker script.