docs(dn): Hongtai_11_22_2025 (#441)

Author: HongtaiDu

src/design_notebooks/2025fall/hd2609.md

@@ -82,11 +82,21 @@ Summary: This week I met with team on Wednesday, which is the weekly meeting in
 
 Summary: This week I spent most of the time on debugging the VScode. I plan to understand the rest of the code in lab 5 next week.
 
-## Week of November 2nd
+## Week of November 9th
 
 ### Project Work
 
 * Did more Verilog practice questions on the HDLBits. I finished until "Case statement" problem.
-* I tested more codes until title "Parameterized Modules & Interfaces". I feel I am still confused by interface and modport. I understand the concepts in Verilog. interfaces group related signals together and modports define directional views of those signals. I am still confused by how they worked together in Verilog. I think need some simple examples on illustrating them.
+* I tested more codes until title "Parameterized Modules & Interfaces". I feel I am still confused by interface and modport. I understand the concepts in Verilog. Interfaces group related signals together and modports define directional views of those signals. I am still confused by how they worked together in Verilog. I think need some simple examples on illustrating them.
 
 Summary: This week I spent most of the time testing the code and understanding concepts in lab 5. I will finish lab 5 next week. Also, I plan to finish lab 7 next week since I see lab 7 is mainly readings, not coding.
+
+## Week of November 16th
+
+### Project Work
+
+* Did more Verilog practice questions on the HDLBits. I finished until "Avoiding Latches" problem.
+* I finished lab 5. I read some documents of Verilog online and figured out meanings of "interface and modport". I also like how the author of lab 5 explained parameters, such as the difference between "reg" and "logic", which gives me deeper understanding of how Verilog works.
+* I also finsihed reading lab 7. It is about The RISC-V ISA specifications. I did not go deeper of that. It seems it is similar to ARM or x86. They are all instruction set architecture, but RISC-V is open-source. If I have time, I would like to know more about RISC-V ISA and maybe find a project to work on in the future.
+
+Summary: I completed all current avaliable labs now. I talked to Darren and would like to challenge myself to finish RiSC-16 chip project on my own because I did program counter and register files last semester. Now, with more knowledge about Verilog, I could try finish other parts. If given time, I will try develop testbench code or ask leader for it.