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</div><div class="wy-menu wy-menu-vertical" data-spy="affix" role="navigation" aria-label="Navigation menu">
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<p class="caption" role="heading"><span class="caption-text">OSVVM Overview</span></p>
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<ul class="current">
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<li class="toctree-l1 current"><a class="current reference internal" href="#">About OSVVM</a></li>
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<li class="toctree-l1"><a class="reference internal" href="Osvvm2GettingStarted.html">Getting Started with OSVVM</a></li>
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<li class="toctree-l1"><a class="reference internal" href="Osvvm3Reports.html">OSVVM Reports</a></li>
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<li class="toctree-l1"><a class="reference internal" href="Osvvm4VerificationFramework.html">Structured Testbench Framework</a></li>
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<li class="toctree-l1"><a class="reference internal" href="Osvvm5UtilityLibrary.html">VHDL Utility Library</a></li>
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<li class="toctree-l1"><a class="reference internal" href="Osvvm6ScriptLibrary.html">Scripting Library</a></li>
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<li class="toctree-l1"><a class="reference internal" href="Osvvm7VerificationComponentLibrary.html">OSVVM Verification Component Library</a></li>
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</ul>
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<p class="caption" role="heading"><span class="caption-text">Appendix</span></p>
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<ul>
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<li class="toctree-l1"><a class="reference internal" href="../genindex.html">Index</a></li>
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<div role="main" class="document" itemscope="itemscope" itemtype="http://schema.org/Article">
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<section id="about-osvvm">
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<h1>About OSVVM<a class="headerlink" href="#about-osvvm" title="Link to this heading"></a></h1>
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<a class="reference external image-reference" href="https://github.com/OSVVM"><img alt="../_images/logo_full_size.png" class="align-center" src="../_images/logo_full_size.png" style="width: 500px;" /></a>
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<section id="id1">
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<h2>About OSVVM<a class="headerlink" href="#id1" title="Link to this heading"></a></h2>
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<p>OSVVM is an advanced verification methodology that
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defines a VHDL verification framework, verification utility library,
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verification component library, scripting API, and co-simulation capability
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that simplifies your FPGA or ASIC verification project from start to finish.
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Using these libraries you can create a simple, readable,
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and powerful testbench that will boost productivity for either
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low level block tests (unit tests) or complex FPGA and ASIC tests.</p>
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<p>OSVVM is developed by the same VHDL experts who
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have helped develop VHDL standards.
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We have used our expert VHDL skills to create
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advanced verification capabilities that provide:</p>
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<p><strong>A structured transaction-based framework</strong></p>
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<ul class="simple">
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<li><p>Suitable for all verification tasks – from Unit/RTL to full
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chip/system level tests.</p></li>
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<li><p>Similar block diagram to SystemVerilog + UVM, except It plugs
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together just like RTL</p></li>
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<li><p>Facilitates re-use of VC and test cases through all levels of testing
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(RTL to Full Chip)</p></li>
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</ul>
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<p><strong>Model Independent Transaction (MIT) Library</strong></p>
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<ul class="simple">
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<li><p>Defines Transaction API - procedures called by test case to build up
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sequences of interface operations - such as send, get, write, read</p></li>
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<li><p>Defines Transaction Interface - connects Verification Component to
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Test Sequencer.</p></li>
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<li><p>Used by all OSVVM defined VC</p></li>
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</ul>
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<p><strong>Simplified Verification component (VC) development</strong></p>
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<ul class="simple">
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<li><p>Uses MIT library = building block level re-use.</p></li>
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<li><p>Makes development of a VC as simple as writing a procedure.</p></li>
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<li><p>No OO or fork and join - uses natural concurrency of a VHDL
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entity/architecture</p></li>
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<li><p>Any VHDL engineer can do this</p></li>
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</ul>
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<p><strong>Readable Test cases</strong></p>
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<ul class="simple">
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<li><p>Simplified since all VC of a similar type implement a subset of the
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MIT transaction calls (send, get, …)</p></li>
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<li><p>Directed tests or complex, randomized tests can be written by any
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VHDL engineer</p></li>
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<li><p>Readable and reviewable by the whole team including software and
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system engineers.</p></li>
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</ul>
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<p><strong>Unmatched Test Reports</strong></p>
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<ul class="simple">
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<li><p>Build Summary - HTML (for humans) + JUnit XML (for CI tools)</p></li>
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<li><p>Test Cases - HTML</p></li>
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<li><p>Logs - HTML + plain text</p></li>
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<li><p>Requirements Tracking - HTML + CSV</p></li>
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<li><p>Helps Find and Debug issues faster</p></li>
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</ul>
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<p><strong>Powerful verification utilities that make VHDL a full verification
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language, including</strong></p>
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<ul class="simple">
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<li><p>Constrained Random, Functional Coverage, Scoreboards, FIFOs, Memory
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Models, error logging and reporting (alerts), and message filtering
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(logs).</p></li>
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<li><p>Capabilities are simple to use, concise, and work like built-in
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language features.</p></li>
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</ul>
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<p><strong>Requirements Tracking</strong></p>
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<ul class="simple">
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<li><p>Tracked using both OSVVM’s affirmations and functional coverage</p></li>
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<li><p>Tracks a count of each requirement and not just a boolean type check.</p></li>
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</ul>
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<p><strong>A Common Scripting API</strong></p>
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<ul class="simple">
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<li><p>Same script runs all simulators – including GHDL, NVC, Aldec
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Riviera-PRO and ActiveHDL, Siemens Questa and ModelSim, Synopsys VCS,
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Cadence Xcelium, and Xilinx XSIM.</p></li>
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<li><p>Is an API on top of Tcl</p></li>
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<li><p>Most scripts are just slightly more than a list of files</p></li>
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<li><p>Can run Tcl when you need it - usually no Tcl is required</p></li>
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</ul>
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<p><strong>Free, Open Source Verification Components include</strong></p>
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<ul class="simple">
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<li><p>AXI Full and Lite, AxiStream, Wishbone, UART, xMII, SPI, DpRam,
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VideoBus.</p></li>
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</ul>
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<p><strong>Co-simulation</strong></p>
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<ul class="simple">
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<li><p>Supports running software (C++) in a hardware simulation environment.</p></li>
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<li><p>Write test cases in C++</p></li>
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<li><p>Run C++ models such as instruct set simulators</p></li>
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</ul>
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<p><strong>Architected by a long-time IEEE VHDL working group contributor</strong></p>
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<ul class="simple">
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<li><p>So expect better VHDL implementations.</p></li>
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</ul>
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<p><strong>It is Free, Open Source under APACHE 2.0</strong></p>
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<ul class="simple">
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<li><p>Upgrades an ordinary VHDL license to a full featured verification
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capabilities</p></li>
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<li><p><a class="reference external" href="https://github.com/osvvm/OsvvmLibraries">On GitHub</a> and IEEE Open
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Source.</p></li>
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<li><p>We accept issues and pull requests on GitHub.</p></li>
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<li><p>Join us.</p></li>
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</ul>
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<p><strong>Get similar verification capabilities to SystemVerilog + UVM without needing OO.</strong></p>
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<p>Looking to improve your VHDL verification methodology?
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OSVVM provides a complete solution for VHDL ASIC or FPGA verification.
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There is no new language to learn.
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It is simple, powerful, and concise.
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Each piece can be used separately.
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Hence, you can learn and adopt pieces as you need them.</p>
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<p>SynthWorks has been using OSVVM for 25+ years in our
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training classes and consulting work.
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During that time, we have innovated new capabilities
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and evolved our existing ones to increase
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re-use and reduce effort and time spent.</p>
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</section>
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‎Overview/Osvvm2GettingStarted.html‎

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2022.03
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<p class="caption" role="heading"><span class="caption-text">OSVVM Overview</span></p>
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<li class="toctree-l1"><a class="reference internal" href="Osvvm1About.html">About OSVVM</a></li>
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<li class="toctree-l1 current"><a class="current reference internal" href="#">Getting Started with OSVVM</a></li>
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<li class="toctree-l1"><a class="reference internal" href="Osvvm3Reports.html">OSVVM Reports</a></li>
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<li class="toctree-l1"><a class="reference internal" href="Osvvm4VerificationFramework.html">Structured Testbench Framework</a></li>
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<li class="toctree-l1"><a class="reference internal" href="Osvvm5UtilityLibrary.html">VHDL Utility Library</a></li>
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<li class="toctree-l1"><a class="reference internal" href="Osvvm6ScriptLibrary.html">Scripting Library</a></li>
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<li class="toctree-l1"><a class="reference internal" href="Osvvm7VerificationComponentLibrary.html">OSVVM Verification Component Library</a></li>
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</ul>
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<p class="caption" role="heading"><span class="caption-text">Appendix</span></p>
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<section id="getting-started-with-osvvm">
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<h1>Getting Started with OSVVM<a class="headerlink" href="#getting-started-with-osvvm" title="Link to this heading"></a></h1>
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<section id="id1">
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<h2>Getting Started with OSVVM<a class="headerlink" href="#id1" title="Link to this heading"></a></h2>
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<p>The best way to get started with OSVVM is to run the demo examples.</p>
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<section id="download-osvvm">
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<h3>Download OSVVM<a class="headerlink" href="#download-osvvm" title="Link to this heading"></a></h3>
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<p>OSVVM is available as either a git repository <a class="reference external" href="https://github.com/OSVVM/OsvvmLibraries">OsvvmLibraries</a> or
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a zip file from <a class="reference external" href="https://osvvm.org/downloads/">OSVVM Downloads Page</a>.</p>
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<p>On GitHub, all OSVVM libraries are a submodule of the repository <a class="reference external" href="https://github.com/OSVVM/OsvvmLibraries">OsvvmLibraries</a>.
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Download all OSVVM libraries using git clone with the “–recursive” flag:</p>
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<div class="highlight-default notranslate"><div class="highlight"><pre><span></span>$ git clone --recursive https://GitHub.com/OSVVM/OsvvmLibraries
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</pre></div>
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</div>
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</section>
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<section id="running-the-demos">
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<h3>Running the Demos<a class="headerlink" href="#running-the-demos" title="Link to this heading"></a></h3>
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<p>A great way to get oriented with OSVVM is to run the demos.</p>
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<p>If you are using Aldec’s Rivera-PRO or Siemen’s QuestaSim/ModelSim do the following.</p>
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<ul class="simple">
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<li><p>Step 1: Create a directory named sim that is in the same directory that contains the OsvvmLibraries directory.</p></li>
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<li><p>Step 2: Start your simulator and go to the sim directory.</p></li>
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<li><p>Step 3: Do the following in your simulator command line:</p></li>
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</ul>
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<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">source</span> <span class="o">../</span><span class="n">OsvvmLibraries</span><span class="o">/</span><span class="n">Scripts</span><span class="o">/</span><span class="n">StartUp</span><span class="o">.</span><span class="n">tcl</span>
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<span class="n">build</span> <span class="o">../</span><span class="n">OsvvmLibraries</span>
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<span class="n">build</span> <span class="o">../</span><span class="n">OsvvmLibraries</span><span class="o">/</span><span class="n">RunDemoTests</span><span class="o">.</span><span class="n">pro</span>
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</pre></div>
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</div>
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<p>These will produce some reports, such as OsvvmLibraries_RunDemoTests.html.
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We will discuss these in the next section, OSVVM Reports.</p>
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<p>If you are using GHDL, Aldec Active-HDL, Synopsys VCS, or
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Cadence Xcelium, see the OSVVM Script User Guide for details on
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running the scripts in these tool.
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The start up aspect for each of these is slightly different, however,
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once you get the simulator into OSVVM script mode, running the scripts
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is the same.</p>
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</section>
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