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SWDEV-179954 - OpenCL/LC - Merge branch amd-master into amd-common
Change-Id: Id6a4d78722aaa0ae35c754c22e5a5ae2854610bf
2 parents f4b2516 + 24a2914 commit e29fb18

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‎README.txt‎

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@@ -15,3 +15,4 @@ documentation setup.
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If you are writing a package for LLVM, see docs/Packaging.rst for our
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suggestions.
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‎docs/FAQ.rst‎

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@@ -9,17 +9,10 @@ Frequently Asked Questions (FAQ)
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License
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=======
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Does the University of Illinois Open Source License really qualify as an "open source" license?
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-----------------------------------------------------------------------------------------------
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Yes, the license is `certified
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<http://www.opensource.org/licenses/UoI-NCSA.php>`_ by the Open Source
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Initiative (OSI).
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Can I modify LLVM source code and redistribute the modified source?
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-------------------------------------------------------------------
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Yes. The modified source distribution must retain the copyright notice and
22-
follow the three bulleted conditions listed in the `LLVM license
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follow the conditions listed in the `LLVM license
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<http://llvm.org/svn/llvm-project/llvm/trunk/LICENSE.TXT>`_.
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@@ -41,10 +34,12 @@ the STL.
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How portable is the LLVM source code?
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-------------------------------------
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The LLVM source code should be portable to most modern Unix-like operating
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systems. Most of the code is written in standard C++ with operating system
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systems. LLVM has also excellent support on Windows systems.
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Most of the code is written in standard C++ with operating system
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services abstracted to a support library. The tools required to build and
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test LLVM have been ported to a plethora of platforms.
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What API do I use to store a value to one of the virtual registers in LLVM IR's SSA representation?
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---------------------------------------------------------------------------------------------------
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‎include/llvm/CodeGen/MIRYamlMapping.h‎

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@@ -314,6 +314,7 @@ struct ScalarEnumerationTraits<TargetStackID::Value> {
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static void enumeration(yaml::IO &IO, TargetStackID::Value &ID) {
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IO.enumCase(ID, "default", TargetStackID::Default);
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IO.enumCase(ID, "sgpr-spill", TargetStackID::SGPRSpill);
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IO.enumCase(ID, "sve-vec", TargetStackID::SVEVector);
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IO.enumCase(ID, "noalloc", TargetStackID::NoAlloc);
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}
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};

‎include/llvm/CodeGen/TargetFrameLowering.h‎

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@@ -28,6 +28,7 @@ namespace TargetStackID {
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enum Value {
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Default = 0,
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SGPRSpill = 1,
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SVEVector = 2,
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NoAlloc = 255
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};
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}

‎include/llvm/IR/IRBuilder.h‎

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@@ -1649,7 +1649,7 @@ class IRBuilder : public IRBuilderBase, public Inserter {
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StoreInst *CreateAlignedStore(Value *Val, Value *Ptr, unsigned Align,
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bool isVolatile = false) {
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StoreInst *SI = CreateStore(Val, Ptr, isVolatile);
1652-
SI->setAlignment(Align);
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SI->setAlignment(MaybeAlign(Align));
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return SI;
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}
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‎include/llvm/IR/Instructions.h‎

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@@ -374,8 +374,6 @@ class StoreInst : public Instruction {
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return 0;
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}
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// FIXME: Remove once migration to Align is over.
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void setAlignment(unsigned Align);
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void setAlignment(MaybeAlign Align);
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/// Returns the ordering constraint of this store instruction.

‎include/llvm/IR/IntrinsicsAMDGPU.td‎

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@@ -899,7 +899,10 @@ class AMDGPURawBufferLoad<LLVMType data_ty = llvm_any_ty> : Intrinsic <
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[llvm_v4i32_ty, // rsrc(SGPR)
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llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
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llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
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llvm_i32_ty], // cachepolicy(imm; bit 0 = glc, bit 1 = slc, bit 2 = dlc on gfx10+)
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llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc,
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// bit 1 = slc,
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// bit 2 = dlc on gfx10+),
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// swizzled buffer (bit 3 = swz))
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[IntrReadMem, ImmArg<3>], "", [SDNPMemOperand]>,
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AMDGPURsrcIntrinsic<0>;
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def int_amdgcn_raw_buffer_load_format : AMDGPURawBufferLoad<llvm_anyfloat_ty>;
@@ -911,7 +914,10 @@ class AMDGPUStructBufferLoad<LLVMType data_ty = llvm_any_ty> : Intrinsic <
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llvm_i32_ty, // vindex(VGPR)
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llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
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llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
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llvm_i32_ty], // cachepolicy(imm; bit 0 = glc, bit 1 = slc, bit 2 = dlc on gfx10+)
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llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc,
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// bit 1 = slc,
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// bit 2 = dlc on gfx10+),
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// swizzled buffer (bit 3 = swz))
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[IntrReadMem, ImmArg<4>], "", [SDNPMemOperand]>,
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AMDGPURsrcIntrinsic<0>;
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def int_amdgcn_struct_buffer_load_format : AMDGPUStructBufferLoad<llvm_anyfloat_ty>;
@@ -923,7 +929,10 @@ class AMDGPURawBufferStore<LLVMType data_ty = llvm_any_ty> : Intrinsic <
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llvm_v4i32_ty, // rsrc(SGPR)
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llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
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llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
926-
llvm_i32_ty], // cachepolicy(imm; bit 0 = glc, bit 1 = slc, bit 2 = dlc on gfx10+)
932+
llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc,
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// bit 1 = slc,
934+
// bit 2 = dlc on gfx10+),
935+
// swizzled buffer (bit 3 = swz))
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[IntrWriteMem, ImmArg<4>], "", [SDNPMemOperand]>,
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AMDGPURsrcIntrinsic<1>;
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def int_amdgcn_raw_buffer_store_format : AMDGPURawBufferStore<llvm_anyfloat_ty>;
@@ -936,7 +945,10 @@ class AMDGPUStructBufferStore<LLVMType data_ty = llvm_any_ty> : Intrinsic <
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llvm_i32_ty, // vindex(VGPR)
937946
llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
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llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
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llvm_i32_ty], // cachepolicy(imm; bit 0 = glc, bit 1 = slc, bit 2 = dlc on gfx10+)
948+
llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc,
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// bit 1 = slc,
950+
// bit 2 = dlc on gfx10+),
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// swizzled buffer (bit 3 = swz))
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[IntrWriteMem, ImmArg<5>], "", [SDNPMemOperand]>,
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AMDGPURsrcIntrinsic<1>;
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def int_amdgcn_struct_buffer_store_format : AMDGPUStructBufferStore<llvm_anyfloat_ty>;
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llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
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llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
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llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt)
1053-
llvm_i32_ty], // cachepolicy(imm; bit 0 = glc, bit 1 = slc, bit 2 = dlc on gfx10+)
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llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc,
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// bit 1 = slc,
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// bit 2 = dlc on gfx10+),
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// swizzled buffer (bit 3 = swz))
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[IntrReadMem, ImmArg<3>, ImmArg<4>], "", [SDNPMemOperand]>,
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AMDGPURsrcIntrinsic<0>;
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llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
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llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
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llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt)
1064-
llvm_i32_ty], // cachepolicy(imm; bit 0 = glc, bit 1 = slc, bit 2 = dlc on gfx10+)
1079+
llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc,
1080+
// bit 1 = slc,
1081+
// bit 2 = dlc on gfx10+),
1082+
// swizzled buffer (bit 3 = swz))
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[IntrWriteMem, ImmArg<4>, ImmArg<5>], "", [SDNPMemOperand]>,
10661084
AMDGPURsrcIntrinsic<1>;
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@@ -1072,7 +1090,10 @@ def int_amdgcn_struct_tbuffer_load : Intrinsic <
10721090
llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
10731091
llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
10741092
llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt)
1075-
llvm_i32_ty], // cachepolicy(imm; bit 0 = glc, bit 1 = slc, bit 2 = dlc on gfx10+)
1093+
llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc,
1094+
// bit 1 = slc,
1095+
// bit 2 = dlc on gfx10+),
1096+
// swizzled buffer (bit 3 = swz))
10761097
[IntrReadMem, ImmArg<4>, ImmArg<5>], "", [SDNPMemOperand]>,
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AMDGPURsrcIntrinsic<0>;
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@@ -1084,7 +1105,10 @@ def int_amdgcn_struct_tbuffer_store : Intrinsic <
10841105
llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
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llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
10861107
llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt)
1087-
llvm_i32_ty], // cachepolicy(imm; bit 0 = glc, bit 1 = slc, bit 2 = dlc on gfx10+)
1108+
llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc,
1109+
// bit 1 = slc,
1110+
// bit 2 = dlc on gfx10+),
1111+
// swizzled buffer (bit 3 = swz))
10881112
[IntrWriteMem, ImmArg<5>, ImmArg<6>], "", [SDNPMemOperand]>,
10891113
AMDGPURsrcIntrinsic<1>;
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‎include/llvm/ObjectYAML/ELFYAML.h‎

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@@ -137,7 +137,8 @@ struct Section {
137137
StackSizes,
138138
SymtabShndxSection,
139139
Symver,
140-
MipsABIFlags
140+
MipsABIFlags,
141+
Addrsig
141142
};
142143
SectionKind Kind;
143144
StringRef Name;
@@ -256,6 +257,26 @@ struct VerneedSection : Section {
256257
}
257258
};
258259

260+
struct AddrsigSymbol {
261+
AddrsigSymbol(StringRef N) : Name(N), Index(None) {}
262+
AddrsigSymbol(llvm::yaml::Hex32 Ndx) : Name(None), Index(Ndx) {}
263+
AddrsigSymbol() : Name(None), Index(None) {}
264+
265+
Optional<StringRef> Name;
266+
Optional<llvm::yaml::Hex32> Index;
267+
};
268+
269+
struct AddrsigSection : Section {
270+
Optional<yaml::BinaryRef> Content;
271+
Optional<llvm::yaml::Hex64> Size;
272+
Optional<std::vector<AddrsigSymbol>> Symbols;
273+
274+
AddrsigSection() : Section(SectionKind::Addrsig) {}
275+
static bool classof(const Section *S) {
276+
return S->Kind == SectionKind::Addrsig;
277+
}
278+
};
279+
259280
struct SymverSection : Section {
260281
std::vector<uint16_t> Entries;
261282

@@ -362,6 +383,7 @@ struct Object {
362383
} // end namespace ELFYAML
363384
} // end namespace llvm
364385

386+
LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::ELFYAML::AddrsigSymbol)
365387
LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::ELFYAML::StackSizeEntry)
366388
LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::ELFYAML::DynamicEntry)
367389
LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::ELFYAML::ProgramHeader)
@@ -518,6 +540,10 @@ template <> struct MappingTraits<ELFYAML::VernauxEntry> {
518540
static void mapping(IO &IO, ELFYAML::VernauxEntry &E);
519541
};
520542

543+
template <> struct MappingTraits<ELFYAML::AddrsigSymbol> {
544+
static void mapping(IO &IO, ELFYAML::AddrsigSymbol &Sym);
545+
};
546+
521547
template <> struct MappingTraits<ELFYAML::Relocation> {
522548
static void mapping(IO &IO, ELFYAML::Relocation &Rel);
523549
};

‎include/llvm/Target/GlobalISel/Combine.td‎

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1+
//===- Combine.td - Combine rule definitions ---------------*- tablegen -*-===//
2+
//
3+
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4+
// See https://llvm.org/LICENSE.txt for license information.
5+
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
//
7+
//===----------------------------------------------------------------------===//
8+
//
9+
// Declare GlobalISel combine rules and provide mechanisms to opt-out.
10+
//
11+
//===----------------------------------------------------------------------===//
12+
13+
// Declares a combiner helper class
14+
class GICombinerHelper<string classname> {
15+
// The class name to use in the generated output.
16+
string Classname = classname;
17+
}

‎include/llvm/Transforms/Utils/SimplifyLibCalls.h‎

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@@ -181,6 +181,7 @@ class LibCallSimplifier {
181181
Value *optimizeMemSet(CallInst *CI, IRBuilder<> &B);
182182
Value *optimizeRealloc(CallInst *CI, IRBuilder<> &B);
183183
Value *optimizeWcslen(CallInst *CI, IRBuilder<> &B);
184+
Value *optimizeBCopy(CallInst *CI, IRBuilder<> &B);
184185
// Wrapper for all String/Memory Library Call Optimizations
185186
Value *optimizeStringMemoryLibCall(CallInst *CI, IRBuilder<> &B);
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