am261x: enet: Add CPSW Clock config

- Add CPSW Clock config
-Fix CAN DMA Example

Fixes: MCUSDK-14156

Signed-off-by: Ashwin Raj <[email protected]>

Author: ashwin-ti

examples/drivers/mcan/canfd_loopback_dma/am261x-lp/r5fss0-0_nortos/example.syscfg

@@ -44,9 +44,13 @@ const dma_trig_xbar2  = dma_trig_xbar.addInstance();
 /**
  * Write custom configuration values to the imported modules.
  */
-mcan1.$name        = "CONFIG_MCAN0";
-mcan1.sdkInfra     = "HLD";
-mcan1.MCAN.$assign = "MCAN1";
+mcan1.$name               = "CONFIG_MCAN0";
+mcan1.sdkInfra            = "HLD";
+mcan1.operMode            = "DMA";
+mcan1.transferMode        = "CALLBACK";
+mcan1.transferCallbackFxn = "App_CANFDTransferCallback";
+mcan1.errorCallbackFxn    = "App_CANFDErrorCallback";
+mcan1.MCAN.$assign        = "MCAN1";
 
 const edma                  = scripting.addModule("/drivers/edma/edma", {}, false);
 const edma1                 = edma.addInstance({}, false);

source/drivers/soc/am261x/soc_rcm.c

@@ -448,6 +448,31 @@ static uint16_t gCptsClkSrcValMap[] =
     [SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT2]     = UNSUPPORTED_CLOCK_SOURCE,
 };
 
+/**
+ * @brief
+ *  Mapping Array for CPSW_5_50_250
+ *
+ * @details
+ *  Mapping Array between Clock mode and Clock Mode Value for CPSW_5_50_250
+ */
+static uint16_t gCpswClkSrcValMap[] =
+{
+    [SOC_RcmPeripheralClockSource_XTALCLK]                     = 0x111U,
+    [SOC_RcmPeripheralClockSource_SYS_CLK]                     = 0x222U,
+    [SOC_RcmPeripheralClockSource_WUCPUCLK]                    = 0x000U,
+    [SOC_RcmPeripheralClockSource_EXT_REFCLK]                  = 0x666U,
+    [SOC_RcmPeripheralClockSource_RCCLK10M]                    = 0x555U,
+    [SOC_RcmPeripheralClockSource_RCCLK32K]                    = UNSUPPORTED_CLOCK_SOURCE,
+    [SOC_RcmPeripheralClockSource_CTPS_GENF0]                  = UNSUPPORTED_CLOCK_SOURCE,
+    [SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT0]    = UNSUPPORTED_CLOCK_SOURCE,
+    [SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT1]    = 0x333U,
+    [SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT2]    = UNSUPPORTED_CLOCK_SOURCE,
+    [SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT3]    = UNSUPPORTED_CLOCK_SOURCE,
+    [SOC_RcmPeripheralClockSource_DPLL_ETH_HSDIV0_CLKOUT0]     = 0x444U,
+    [SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT0]     = UNSUPPORTED_CLOCK_SOURCE,
+    [SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT2]     = UNSUPPORTED_CLOCK_SOURCE,
+};
+
 /**
  * @brief
  *  Mapping Array for GPMC
@@ -1087,6 +1112,13 @@ static void SOC_rcmGetClkSrcAndDivReg (SOC_RcmPeripheralId periphId,
             *clkSrcVal = gIcssmUartClkSrcValMap[clkSource];
             break;
         }
+        case SOC_RcmPeripheralId_CPSW_5_50_250:
+        {
+            *clkSrcReg  = &(ptrMSSRCMRegs->CPSW_5_50_250_CLK_MUX_CTRL);
+            *clkdDivReg = NULL; /* No Divisor register for CPSW */
+            *clkSrcVal = gCpswClkSrcValMap[clkSource];
+            break;
+        }
         case SOC_RcmPeripheralId_CPTS:
         {
             *clkSrcReg  = &(ptrMSSRCMRegs->CPTS_CLK_SRC_SEL);
@@ -2368,25 +2400,43 @@ int32_t SOC_rcmSetPeripheralClock (SOC_RcmPeripheralId periphId,
     clkDivisor = SOC_rcmGetModuleClkDivVal(Finp, freqHz);
     SOC_rcmGetClkSrcAndDivReg (periphId, clkSource, &clkSrcVal, &ptrClkSrcReg, &ptrClkDivReg);
 
-    if ((ptrClkSrcReg != NULL) && (ptrClkDivReg != NULL) && (clkSrcVal != 0x888U))
+    if(periphId == SOC_RcmPeripheralId_CPSW_5_50_250)
     {
-        uint16_t            clkDivVal;
-
-        /* Create the Divider Value to be programmed */
-        clkDivVal = ((uint16_t)clkDivisor & 0xFU);
-        clkDivVal = (clkDivVal | (clkDivVal << 4U) | (clkDivVal << 8U));
-
-        /* Write the Divider Value */
-        *ptrClkDivReg = SOC_rcmInsert16 (*ptrClkDivReg, 11U, 0U, clkDivVal);
-
-        /* Write the Clock Source Selection Value */
-        *ptrClkSrcReg = SOC_rcmInsert16 (*ptrClkSrcReg, 11U, 0U, clkSrcVal);
-        retVal = SystemP_SUCCESS;
+        /* CPSW Clock doesn't have Sel and Div registers. It has Mux register which is passed as Sel. */
+        if ((ptrClkSrcReg != NULL) && (clkSrcVal != 0x888U))
+        {
+            /* Write the Clock Mux Value */
+            *ptrClkSrcReg = SOC_rcmInsert16 (*ptrClkSrcReg, 11U, 0U, clkSrcVal);
+            retVal = SystemP_SUCCESS;
+        }
+        else
+        {
+            /* Error */
+            retVal = SystemP_FAILURE;
+        }
     }
     else
     {
-        /* Error */
-        retVal = SystemP_FAILURE;
+        if ((ptrClkSrcReg != NULL) && (ptrClkDivReg != NULL) && (clkSrcVal != 0x888U))
+        {
+            uint16_t            clkDivVal;
+
+            /* Create the Divider Value to be programmed */
+            clkDivVal = ((uint16_t)clkDivisor & 0xFU);
+            clkDivVal = (clkDivVal | (clkDivVal << 4U) | (clkDivVal << 8U));
+
+            /* Write the Divider Value */
+            *ptrClkDivReg = SOC_rcmInsert16 (*ptrClkDivReg, 11U, 0U, clkDivVal);
+
+            /* Write the Clock Source Selection Value */
+            *ptrClkSrcReg = SOC_rcmInsert16 (*ptrClkSrcReg, 11U, 0U, clkSrcVal);
+            retVal = SystemP_SUCCESS;
+        }
+        else
+        {
+            /* Error */
+            retVal = SystemP_FAILURE;
+        }
     }
 
     return (retVal);
@@ -2700,6 +2750,11 @@ int32_t SOC_rcmEnablePeripheralClock(SOC_RcmPeripheralId periphId, uint32_t enab
             }
             break;
         }
+        case SOC_RcmPeripheralId_CPSW_5_50_250:
+        {
+            /* Do nothing since there is no GATE register */
+            break;
+        }
         case SOC_RcmPeripheralId_GPMC:
         {
             if(enable==1)

source/drivers/soc/am261x/soc_rcm.h

@@ -387,6 +387,10 @@ typedef enum SOC_RcmPeripheralId_e
      * \brief   Value specifying CPTS
      */
     SOC_RcmPeripheralId_CPTS,
+    /**
+     * \brief   Value specifying CPSW_5_50_250
+     */
+    SOC_RcmPeripheralId_CPSW_5_50_250,
     /**
      * \brief   Value specifying GPMC
      */