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Add look ahead interface for working COMPRESSED
and some other additions to the example: Add simple start.S with minimal trap handler (see https://github.com/cliffordwolf/picorv32/blob/master/firmware/start.S for a bigger version) Add irq interface to attosoc.v for working debug() in picorv32.v Add printf from https://github.com/mpaland/printf Use SITE "L19" for uart output Signed-off-by: Tom Vijlbrief <[email protected]>
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14 files changed

+963
-33
lines changed

‎examples/soc_ecp5_evn/Makefile‎

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,15 @@
1-
firmware.elf: sections.lds start.s firmware.c
2-
riscv32-unknown-elf-gcc -march=rv32i -Wl,-Bstatic,-T,sections.lds,--strip-debug -ffreestanding -nostdlib -o firmware.elf start.s firmware.c
1+
firmware.elf: sections.lds start.S firmware.c printf.c
2+
riscv32-unknown-elf-gcc -march=rv32imc -Os -mabi=ilp32 -Wl,-Bstatic,-T,sections.lds,--strip-debug -ffreestanding -nostdlib -o firmware.elf start.S firmware.c -DPRINTF_DISABLE_SUPPORT_LONG_LONG -DPRINTF_DISABLE_SUPPORT_PTRDIFF_T printf.c -lm -lc -lgcc
3+
#/opt/riscv32imc/bin/riscv32-unknown-elf-gcc -march=rv32imc -Os -mabi=ilp32 -Wl,-Bstatic,-T,sections.lds,--strip-debug -ffreestanding -nostdlib -o firmware.elf start.S firmware.c -DPRINTF_DISABLE_SUPPORT_LONG_LONG -DPRINTF_DISABLE_SUPPORT_PTRDIFF_T printf.c -lm -lc -lgcc
34

45
firmware.bin: firmware.elf
56
riscv32-unknown-elf-objcopy -O binary firmware.elf /dev/stdout > firmware.bin
67

78
firmware.hex: firmware.bin
8-
python3 makehex.py $^ 4096 > $@
9+
python3 makehex.py $^ 16384 > $@
910

10-
attosoc_tb.vvp: attosoc_tb.v attosoc.v picorv32.v simpleuart.v
11-
iverilog -s testbench -o $@ $^
11+
attosoc_tb.vvp: attosoc_tb.v attosoc.v picorv32.v simpleuart.v firmware.hex
12+
iverilog -s testbench -o $@ attosoc_tb.v attosoc.v picorv32.v simpleuart.v
1213

1314
attosoc_sim: attosoc_tb.vvp firmware.hex
1415
vvp -N $<

‎examples/soc_ecp5_evn/attosoc.v‎

Lines changed: 26 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@ module attosoc (
2828
input clk,
2929
output reg [7:0] led,
3030
output uart_tx,
31-
input uart_rx,
31+
input uart_rx
3232
);
3333

3434
reg [5:0] reset_cnt = 0;
@@ -38,7 +38,8 @@ module attosoc (
3838
reset_cnt <= reset_cnt + !resetn;
3939
end
4040

41-
parameter integer MEM_WORDS = 8192;
41+
// parameter integer MEM_WORDS = 8192;
42+
parameter integer MEM_WORDS = 16384;
4243
parameter [31:0] STACKADDR = 32'h 0000_0000 + (4*MEM_WORDS); // end of memory
4344
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000; // start of memory
4445

@@ -47,13 +48,24 @@ module attosoc (
4748
reg [31:0] ram_rdata;
4849
reg ram_ready;
4950

51+
reg [31:0] irq = 32'h 0000_0000;
52+
wire [31:0] eoi;
53+
5054
wire mem_valid;
5155
wire mem_instr;
5256
wire mem_ready;
5357
wire [31:0] mem_addr;
5458
wire [31:0] mem_wdata;
5559
wire [3:0] mem_wstrb;
5660
wire [31:0] mem_rdata;
61+
wire [31:0] mem_la_addr;
62+
wire mem_la_read;
63+
64+
always @(posedge clk)
65+
begin
66+
if (mem_la_read)
67+
ram_rdata <= ram[mem_la_addr[23:2]];
68+
end
5769

5870
always @(posedge clk)
5971
begin
@@ -64,7 +76,7 @@ module attosoc (
6476
if (mem_wstrb[2]) ram[mem_addr[23:2]][23:16] <= mem_wdata[23:16];
6577
if (mem_wstrb[3]) ram[mem_addr[23:2]][31:24] <= mem_wdata[31:24];
6678

67-
ram_rdata <= ram[mem_addr[23:2]];
79+
// ram_rdata <= ram[mem_addr[23:2]];
6880
ram_ready <= 1'b1;
6981
end
7082
end
@@ -107,13 +119,13 @@ module attosoc (
107119
picorv32 #(
108120
.STACKADDR(STACKADDR),
109121
.PROGADDR_RESET(PROGADDR_RESET),
110-
.PROGADDR_IRQ(32'h 0000_0000),
122+
.PROGADDR_IRQ(32'h 0000_0010),
111123
.BARREL_SHIFTER(0),
112-
.COMPRESSED_ISA(0),
113-
.ENABLE_MUL(0),
114-
.ENABLE_DIV(0),
115-
.ENABLE_IRQ(0),
116-
.ENABLE_IRQ_QREGS(0)
124+
.COMPRESSED_ISA(1),
125+
.ENABLE_MUL(1),
126+
.ENABLE_DIV(1),
127+
.ENABLE_IRQ(1),
128+
.ENABLE_IRQ_QREGS(1)
117129
) cpu (
118130
.clk (clk ),
119131
.resetn (resetn ),
@@ -123,7 +135,11 @@ module attosoc (
123135
.mem_addr (mem_addr ),
124136
.mem_wdata (mem_wdata ),
125137
.mem_wstrb (mem_wstrb ),
126-
.mem_rdata (mem_rdata )
138+
.mem_rdata (mem_rdata ),
139+
.irq (irq ),
140+
.eoi (eoi ),
141+
.mem_la_read (mem_la_read),
142+
.mem_la_addr (mem_la_addr)
127143
);
128144

129145
simpleuart simpleuart (

‎examples/soc_ecp5_evn/attosoc_tb.v‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5,10 +5,10 @@ module testbench();
55
always #5 clk = (clk === 1'b0);
66

77
initial begin
8-
$dumpfile("testbench.vcd");
9-
$dumpvars(0, testbench);
8+
// $dumpfile("testbench.vcd");
9+
// $dumpvars(0, testbench);
1010

11-
repeat (10) begin
11+
repeat (4) begin
1212
repeat (50000) @(posedge clk);
1313
$display("+50000 cycles");
1414
end
@@ -18,7 +18,7 @@ module testbench();
1818
wire [7:0] led;
1919

2020
always @(led) begin
21-
#1 $display("%b", led);
21+
#1 $display("LED: %b", led);
2222
end
2323

2424
attosoc uut (

‎examples/soc_ecp5_evn/ecp5evn.lpf‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,8 @@ IOBUF PORT "led[5]" IO_TYPE=LVCMOS25;
1919
IOBUF PORT "led[6]" IO_TYPE=LVCMOS25;
2020
IOBUF PORT "led[7]" IO_TYPE=LVCMOS25;
2121

22-
LOCATE COMP "uart_tx" SITE "P3";
22+
# LOCATE COMP "uart_tx" SITE "P3";
23+
LOCATE COMP "uart_tx" SITE "L19";
2324
LOCATE COMP "uart_rx" SITE "P2";
2425

2526
IOBUF PORT "uart_tx" IO_TYPE=LVCMOS33;

‎examples/soc_ecp5_evn/firmware.c‎

Lines changed: 25 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,21 +1,32 @@
11
#include <stdint.h>
2+
#include <stdlib.h>
3+
#include <math.h>
4+
5+
#include "printf.h"
26

37
#define LED (*(volatile uint32_t*)0x02000000)
48

59
#define reg_uart_clkdiv (*(volatile uint32_t*)0x02000004)
610
#define reg_uart_data (*(volatile uint32_t*)0x02000008)
711

8-
void putchar(char c)
12+
void _putchar(char c)
913
{
1014
if (c == '\n')
11-
putchar('\r');
15+
_putchar('\r');
1216
reg_uart_data = c;
1317
}
1418

19+
#define uartchar _putchar
20+
1521
void print(const char *p)
1622
{
1723
while (*p)
18-
putchar(*(p++));
24+
uartchar(*(p++));
25+
}
26+
27+
void trap()
28+
{
29+
print("TRAP\r\n");
1930
}
2031

2132
void delay() {
@@ -25,11 +36,18 @@ void delay() {
2536

2637
int main() {
2738
reg_uart_clkdiv = 416;
39+
int count = 0;
2840
while (1) {
29-
LED = 0xFF;
30-
print("hello world\n");
31-
delay();
32-
LED = 0x00;
41+
char s[20];
42+
LED = ++count;
43+
#if 0
44+
asm("ebreak");
45+
//*((int*)0xf000000f) = 1;
46+
#endif
47+
//print("hello world\n");
48+
//printf("hello world %d\n", count);
49+
printf("hello printf: %d %f\n", count, sqrt(count));
50+
3351
delay();
3452
}
3553
}

‎examples/soc_ecp5_evn/picorv32.v‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@
2222
// `define DEBUGNETS
2323
// `define DEBUGREGS
2424
// `define DEBUGASM
25-
// `define DEBUG
25+
`define DEBUG
2626

2727
`ifdef DEBUG
2828
`define debug(debug_command) debug_command
@@ -122,6 +122,7 @@ module picorv32 #(
122122
output reg rvfi_trap,
123123
output reg rvfi_halt,
124124
output reg rvfi_intr,
125+
output reg [ 1:0] rvfi_mode,
125126
output reg [ 4:0] rvfi_rs1_addr,
126127
output reg [ 4:0] rvfi_rs2_addr,
127128
output reg [31:0] rvfi_rs1_rdata,
@@ -1533,7 +1534,7 @@ module picorv32 #(
15331534
do_waitirq <= 1;
15341535
end else
15351536
if (decoder_trigger) begin
1536-
`debug($display("-- %-0t", $time);)
1537+
`debug($display("-- %-0t pending:%b", $time, irq_pending);)
15371538
irq_delay <= irq_active;
15381539
reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
15391540
if (ENABLE_TRACE)
@@ -1962,6 +1963,7 @@ module picorv32 #(
19621963
rvfi_trap <= trap;
19631964
rvfi_halt <= trap;
19641965
rvfi_intr <= dbg_irq_enter;
1966+
rvfi_mode <= 3;
19651967

19661968
if (!resetn) begin
19671969
dbg_irq_call <= 0;

‎examples/soc_ecp5_evn/pll.v‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,6 @@ module pll_12_50(input clki, output clko);
2424
.PHASEDIR(1'b0),
2525
.PHASESTEP(1'b0),
2626
.PLLWAKESYNC(1'b0),
27-
.ENCLKOP(1'b0),
27+
.ENCLKOP(1'b0)
2828
);
2929
endmodule

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