I have a design that I have been using with the 256BGA variant of the machxo3d that comes with the machxo3d breakout board, but am now porting it to the QFN72 variant and nextpnr is claiming that the pin does not exist when it does.

My constraint looks like:

LOCATE COMP "uart_ctsn" SITE "14";
IOBUF PORT "uart_ctsn" IO_TYPE=LVCMOS33;

nextpnr-machxo3d with --device LCMXO3D-9400HC-6SG72C produces:

ERROR: IO pin 'uart_ctsn$tr_io' constrained to pin '14', which does not exist for package 'QFN72'.

I thought this may be the same as other similar problems with ECP5 where the pin has special function considerations, but I can't see that there's anything special about this pin:

PAD,Pin/Ball Function,BANK,Dual Function,Differential,High Speed,,I/O Grouping,QFN72,CABGA256,CABGA400,CABGA484,WLCSP69
144,PL30C,3,-,True_OF_PL30D,-,,13,14,R1,U4,V5,-

I do see a pin 14 in https://github.com/YosysHQ/prjtrellis-db/blob/master/MachXO3D/LCMXO3D-9400/iodb.json, any insight into what could be wrong?

If I change the constraint to pin 13 or 12, packing succeeds, though after routing I get an assertion failure:

terminate called after throwing an instance of 'nextpnr_machxo2::assertion_failure'
  what():  Assertion failure: no tile at (0, 29) with type in set (/home/via/dev/nextpnr/machxo2/arch.h:1026)
Aborted

I am assuming these symptoms are related, but should I make a separate issue for the assertion failure (or the pin issue) with nextpnr itself? Thank you.

nextpnr-machxo2 --version
"nextpnr-machxo2" -- Next Generation Place and Route (Version nextpnr-0.8-43-ge642e21f)

and built against prjtrellis fce5a14.