Reworded some DRAM timings.

Author: cyring

corefreq-cli-rsc-en.h

@@ -2242,21 +2242,21 @@
 #define RSC_DDR4_WRWR_SC_CODE		" dgWW"
 #define RSC_DDR4_WRWR_SD_CODE		" drWW"
 #define RSC_DDR4_WRWR_DD_CODE		" ddWW"
-#define RSC_DDR4_RRD_S_CODE		" RRDS"
-#define RSC_DDR4_RRD_L_CODE		" RRDL"
+#define RSC_DDR4_RRD_S_CODE		" RRDs"
+#define RSC_DDR4_RRD_L_CODE		" RRDl"
 #define RSC_DDR4_CKE_CODE		" CKE "
 #define RSC_DDR4_CPDED_CODE		"CPDED"
 #define RSC_DDR4_ECC_CODE		"  ECC"
 
 #define RSC_DDR4_ZEN_CL_CODE		"  CL "
-#define RSC_DDR4_ZEN_RCD_R_CODE 	" RCDR"
-#define RSC_DDR4_ZEN_RCD_W_CODE 	" RCDW"
+#define RSC_DDR4_ZEN_RCD_R_CODE 	" RCDr"
+#define RSC_DDR4_ZEN_RCD_W_CODE 	" RCDw"
 #define RSC_DDR4_ZEN_RP_CODE		"  RP "
 #define RSC_DDR4_ZEN_RAS_CODE		" RAS "
 #define RSC_DDR4_ZEN_RC_CODE		"  RC "
 #define RSC_DDR4_ZEN_FAW_CODE		" FAW "
-#define RSC_DDR4_ZEN_WTR_S_CODE 	" WTRS"
-#define RSC_DDR4_ZEN_WTR_L_CODE 	" WTRL"
+#define RSC_DDR4_ZEN_WTR_S_CODE 	" WTRs"
+#define RSC_DDR4_ZEN_WTR_L_CODE 	" WTRl"
 #define RSC_DDR4_ZEN_WR_CODE		"  WR "
 #define RSC_DDR4_ZEN_RDRD_SCL_CODE	" clRR"
 #define RSC_DDR4_ZEN_WRWR_SCL_CODE	" clWW"