Merge pull request #345 from Silabs-ArjanB/ArjanB_dm_halt_addr_i

Replaced DM_HALTADDRESS parameter by dm_halt_addr_i pin

Author: davideschiavone

rtl/riscv_core.sv

@@ -39,8 +39,7 @@ module riscv_core
 #(
   parameter PULP_CLUSTER        =  0,
   parameter FPU                 =  0,
-  parameter PULP_ZFINX          =  0,
-  parameter DM_HALTADDRESS      = 32'h1A110800
+  parameter PULP_ZFINX          =  0
 )
 (
   // Clock and Reset
@@ -50,8 +49,9 @@ module riscv_core
   input  logic        clock_en_i,    // enable clock, otherwise it is gated
   input  logic        scan_cg_en_i,  // enable all clock gates for testing
 
-  // Core ID, Cluster ID and boot address are considered more or less static
+  // Core ID, Cluster ID, debug mode halt address and boot address are considered more or less static
   input  logic [31:0] boot_addr_i,
+  input  logic [31:0] dm_halt_addr_i,
   input  logic [31:0] hart_id_i,
 
   // Instruction memory interface
@@ -475,8 +475,7 @@ module riscv_core
   #(
     .N_HWLP              ( N_HWLP            ),
     .RDATA_WIDTH         ( INSTR_RDATA_WIDTH ),
-    .FPU                 ( FPU               ),
-    .DM_HALTADDRESS      ( DM_HALTADDRESS    )
+    .FPU                 ( FPU               )
   )
   if_stage_i
   (
@@ -486,6 +485,9 @@ module riscv_core
     // boot address
     .boot_addr_i         ( boot_addr_i[31:1] ),
 
+    // debug mode halt address
+    .dm_halt_addr_i      ( dm_halt_addr_i[31:2] ),
+
     // trap vector location
     .m_trap_base_addr_i  ( mtvec             ),
     .m_trap_base_addrx_i ( mtvecx            ),

rtl/riscv_if_stage.sv

@@ -32,8 +32,7 @@ module riscv_if_stage
 #(
   parameter N_HWLP          = 2,
   parameter RDATA_WIDTH     = 32,
-  parameter FPU             = 0,
-  parameter DM_HALTADDRESS  = 32'h1A110800
+  parameter FPU             = 0
 )
 (
     input  logic        clk,
@@ -44,9 +43,12 @@ module riscv_if_stage
     input  logic [23:0] m_trap_base_addrx_i,
     input  logic [23:0] u_trap_base_addr_i,
     input  logic  [1:0] trap_addr_mux_i,
-    // Used for boot address
+    // Boot address
     input  logic [30:0] boot_addr_i,
 
+    // Debug mode halt address
+    input  logic [29:0] dm_halt_addr_i,
+
     // instruction request control
     input  logic        req_i,
 
@@ -142,7 +144,7 @@ module riscv_if_stage
     unique case (exc_pc_mux_i)
       EXC_PC_EXCEPTION:                        exc_pc = { trap_base_addr, 8'h0 }; //1.10 all the exceptions go to base address
       EXC_PC_IRQ:                              exc_pc = { trap_base_addr, 1'b0, exc_vec_pc_mux_i[4:0], 2'b0 }; // interrupts are vectored
-      EXC_PC_DBD:                              exc_pc = { DM_HALTADDRESS       };
+      EXC_PC_DBD:                              exc_pc = { dm_halt_addr_i, 2'b0 };
       default:;
     endcase
   end

tb/core/riscv_wrapper.sv

@@ -66,8 +66,7 @@ module riscv_wrapper
         #(
           .PULP_CLUSTER(PULP_CLUSTER),
           .FPU(FPU),
-          .PULP_ZFINX(PULP_ZFINX),
-          .DM_HALTADDRESS(DM_HALTADDRESS))
+          .PULP_ZFINX(PULP_ZFINX))
     riscv_core_i
         (
          .clk_i                  ( clk_i                 ),
@@ -77,6 +76,7 @@ module riscv_wrapper
          .scan_cg_en_i           ( 1'b0                  ),
 
          .boot_addr_i            ( BOOT_ADDR             ),
+         .dm_halt_addr_i         ( DM_HALTADDRESS        ),
          .hart_id_i              ( 32'h0                 ),
 
          .instr_addr_o           ( instr_addr            ),