Support for the same geth binary as WOMIR (#113)

lvella · web-flow · commit db4a336a2ced · 2025-11-05T16:14:44.000-03:00
* Managing the stack from the JAAF family instructions.

* Code reuse.

* Frame allocator that can track sparse allocated ranges.

* Persisting WomController across segments.

* Carrying across segments only the values in active frames.

* Fixing memory reset.

* Sharing FP.

* Also saving newly allocated frames.

* Adapting the tests to use AllocateFrame.

* Commented out stack print.

* 32-bit offset in mem ops

* Emitting trap on float instructions.

Instead of panicking.

* Added test program.

* Small things.
diff --git a/extensions/circuit/src/adapters/loadstore.rs b/extensions/circuit/src/adapters/loadstore.rs
@@ -116,8 +116,8 @@ pub struct Rv32LoadStoreReadRecord<F: Field> {
     /// read from mememory for loads
     pub mem_read: Option<RecordId>,
     pub rs1_ptr: F,
-    pub imm: F,
-    pub imm_sign: F,
+    pub imm_hi: F,
+    pub imm_lo: F,
     pub mem_as: F,
     pub mem_ptr_limbs: [u32; 2],
     pub shift_amount: u32,
@@ -384,9 +384,9 @@ impl<F: PrimeField32> VmAdapterChipWom<F> for Rv32LoadStoreAdapterChip<F> {
         let rs1_record = wom.read::<RV32_REGISTER_NUM_LIMBS>(b + fp_f);
 
         let rs1_val = compose(rs1_record.1);
-        let imm = c.as_canonical_u32();
-        let imm_sign = g.as_canonical_u32();
-        let imm_extended = imm + imm_sign * 0xff000000;
+        let imm_lo = c.as_canonical_u32();
+        let imm_hi = g.as_canonical_u32();
+        let imm_extended = imm_lo | imm_hi << 16;
 
         let ptr_val = rs1_val.wrapping_add(imm_extended);
         let shift_amount = ptr_val % 4;
@@ -429,8 +429,8 @@ impl<F: PrimeField32> VmAdapterChipWom<F> for Rv32LoadStoreAdapterChip<F> {
                 rs1_ptr: b,
                 wom_read,
                 mem_read,
-                imm: c,
-                imm_sign: g,
+                imm_lo: c,
+                imm_hi: g,
                 shift_amount,
                 mem_ptr_limbs,
                 mem_as: e,
diff --git a/integration/src/instruction_builder.rs b/integration/src/instruction_builder.rs
@@ -503,146 +503,122 @@ pub fn jump_if_zero<F: PrimeField32>(condition_reg: usize, to_pc_imm: usize) ->
 
 /// LOADW instruction: Load word from memory
 /// rd = MEM[rs1 + imm]
-pub fn loadw<F: PrimeField32>(rd: usize, rs1: usize, imm: i32) -> Instruction<F> {
-    let imm_unsigned = (imm & 0xFFFFFF) as usize;
-    let imm_sign = if imm < 0 { 1 } else { 0 };
-
+pub fn loadw<F: PrimeField32>(rd: usize, rs1: usize, imm: u32) -> Instruction<F> {
     Instruction::new(
         LoadStoreOpcode::LOADW.global_opcode(),
         F::from_canonical_usize(riscv::RV32_REGISTER_NUM_LIMBS * rd), // a: rd
         F::from_canonical_usize(riscv::RV32_REGISTER_NUM_LIMBS * rs1), // b: rs1
-        F::from_canonical_usize(imm_unsigned),                        // c: imm (lower 24 bits)
+        F::from_canonical_u32(imm & 0xFFFF),                          // c: imm (lower 16 bits)
         F::ONE,                                                       // d: register address space
         F::from_canonical_usize(2), // e: memory address space (2 for word)
         F::ONE,                     // f: enabled
-        F::from_canonical_usize(imm_sign), // g: imm sign
+        F::from_canonical_u32(imm >> 16), // g: imm (higher 16 bits)
     )
 }
 
 /// STOREW instruction: Store word to memory
 /// MEM[rs1 + imm] = rs2
-pub fn storew<F: PrimeField32>(value: usize, base_address: usize, imm: i32) -> Instruction<F> {
-    let imm_unsigned = (imm & 0xFFFFFF) as usize;
-    let imm_sign = if imm < 0 { 1 } else { 0 };
-
+pub fn storew<F: PrimeField32>(value: usize, base_address: usize, imm: u32) -> Instruction<F> {
     Instruction::new(
         LoadStoreOpcode::STOREW.global_opcode(),
         F::from_canonical_usize(riscv::RV32_REGISTER_NUM_LIMBS * value), // a: rs2 (data to store)
         F::from_canonical_usize(riscv::RV32_REGISTER_NUM_LIMBS * base_address), // b: rs1 (base address)
-        F::from_canonical_usize(imm_unsigned),                                  // c: imm (offset)
-        F::ONE,                            // d: register address space
-        F::from_canonical_usize(2),        // e: memory address space (2 for word, same as LOADW)
-        F::ONE,                            // f: enabled
-        F::from_canonical_usize(imm_sign), // g: imm sign
+        F::from_canonical_u32(imm & 0xFFFF), // c: imm (lower 16 bits)
+        F::ONE,                              // d: register address space
+        F::from_canonical_usize(2),          // e: memory address space (2 for word)
+        F::ONE,                              // f: enabled
+        F::from_canonical_u32(imm >> 16),    // g: imm (higher 16 bits)
     )
 }
 
 /// LOADB: load byte from memory
 /// rd = MEM[rs1 + imm] (sign-extended)
-pub fn loadb<F: PrimeField32>(rd: usize, rs1: usize, imm: i32) -> Instruction<F> {
-    let imm_unsigned = (imm & 0xFFFFFF) as usize;
-    let imm_sign = if imm < 0 { 1 } else { 0 };
-
+pub fn loadb<F: PrimeField32>(rd: usize, rs1: usize, imm: u32) -> Instruction<F> {
     Instruction::new(
         LoadStoreOpcode::LOADB.global_opcode(),
         F::from_canonical_usize(riscv::RV32_REGISTER_NUM_LIMBS * rd), // a: rd
         F::from_canonical_usize(riscv::RV32_REGISTER_NUM_LIMBS * rs1), // b: rs1
-        F::from_canonical_usize(imm_unsigned),                        // c: imm (lower 24 bits)
+        F::from_canonical_u32(imm & 0xFFFF),                          // c: imm (lower 16 bits)
         F::ONE,                                                       // d: register address space
-        F::from_canonical_usize(2), // e: memory address space (2 for byte, same as word)
+        F::from_canonical_usize(2), // e: memory address space (2 for byte)
         F::ONE,                     // f: enabled
-        F::from_canonical_usize(imm_sign), // g: imm sign
+        F::from_canonical_u32(imm >> 16), // g: imm (higher 16 bits)
     )
 }
 
 /// LOADBU instruction: Load byte unsigned from memory
 /// rd = MEM[rs1 + imm] (zero-extended)
-pub fn loadbu<F: PrimeField32>(rd: usize, rs1: usize, imm: i32) -> Instruction<F> {
-    let imm_unsigned = (imm & 0xFFFFFF) as usize;
-    let imm_sign = if imm < 0 { 1 } else { 0 };
-
+pub fn loadbu<F: PrimeField32>(rd: usize, rs1: usize, imm: u32) -> Instruction<F> {
     Instruction::new(
         LoadStoreOpcode::LOADBU.global_opcode(),
         F::from_canonical_usize(riscv::RV32_REGISTER_NUM_LIMBS * rd), // a: rd
         F::from_canonical_usize(riscv::RV32_REGISTER_NUM_LIMBS * rs1), // b: rs1
-        F::from_canonical_usize(imm_unsigned),                        // c: imm (lower 24 bits)
+        F::from_canonical_u32(imm & 0xFFFF),                          // c: imm (lower 16 bits)
         F::ONE,                                                       // d: register address space
-        F::from_canonical_usize(2), // e: memory address space (2 for byte, same as word)
+        F::from_canonical_usize(2), // e: memory address space (2 for byte)
         F::ONE,                     // f: enabled
-        F::from_canonical_usize(imm_sign), // g: imm sign
+        F::from_canonical_u32(imm >> 16), // g: imm (higher 16 bits)
     )
 }
 
 /// LOADH: load halfword from memory
 /// rd = MEM[rs1 + imm] (sign-extended)
 #[allow(unused)]
-pub fn loadh<F: PrimeField32>(rd: usize, rs1: usize, imm: i32) -> Instruction<F> {
-    let imm_unsigned = (imm & 0xFFFFFF) as usize;
-    let imm_sign = if imm < 0 { 1 } else { 0 };
-
+pub fn loadh<F: PrimeField32>(rd: usize, rs1: usize, imm: u32) -> Instruction<F> {
     Instruction::new(
         LoadStoreOpcode::LOADH.global_opcode(),
         F::from_canonical_usize(riscv::RV32_REGISTER_NUM_LIMBS * rd), // a: rd
         F::from_canonical_usize(riscv::RV32_REGISTER_NUM_LIMBS * rs1), // b: rs1
-        F::from_canonical_usize(imm_unsigned),                        // c: imm (lower 24 bits)
+        F::from_canonical_u32(imm & 0xFFFF),                          // c: imm (lower 16 bits)
         F::ONE,                                                       // d: register address space
-        F::from_canonical_usize(2), // e: memory address space (2 for byte, same as word)
+        F::from_canonical_usize(2), // e: memory address space (2 for halfword)
         F::ONE,                     // f: enabled
-        F::from_canonical_usize(imm_sign), // g: imm sign
+        F::from_canonical_u32(imm >> 16), // g: imm (higher 16 bits)
     )
 }
 
 /// LOADHU instruction: Load halfword unsigned from memory
 /// rd = MEM[rs1 + imm] (zero-extended)
-pub fn loadhu<F: PrimeField32>(rd: usize, rs1: usize, imm: i32) -> Instruction<F> {
-    let imm_unsigned = (imm & 0xFFFFFF) as usize;
-    let imm_sign = if imm < 0 { 1 } else { 0 };
-
+pub fn loadhu<F: PrimeField32>(rd: usize, rs1: usize, imm: u32) -> Instruction<F> {
     Instruction::new(
         LoadStoreOpcode::LOADHU.global_opcode(),
         F::from_canonical_usize(riscv::RV32_REGISTER_NUM_LIMBS * rd), // a: rd
         F::from_canonical_usize(riscv::RV32_REGISTER_NUM_LIMBS * rs1), // b: rs1
-        F::from_canonical_usize(imm_unsigned),                        // c: imm (lower 24 bits)
+        F::from_canonical_u32(imm & 0xFFFF),                          // c: imm (lower 16 bits)
         F::ONE,                                                       // d: register address space
-        F::from_canonical_usize(2), // e: memory address space (2 for halfword, same as word)
+        F::from_canonical_usize(2), // e: memory address space (2 for halfword)
         F::ONE,                     // f: enabled
-        F::from_canonical_usize(imm_sign), // g: imm sign
+        F::from_canonical_u32(imm >> 16), // g: imm (higher 16 bits)
     )
 }
 
 /// STOREB instruction: Store byte to memory
 /// MEM[rs1 + imm] = rs2 (lowest byte)
-pub fn storeb<F: PrimeField32>(rs2: usize, rs1: usize, imm: i32) -> Instruction<F> {
-    let imm_unsigned = (imm & 0xFFFFFF) as usize;
-    let imm_sign = if imm < 0 { 1 } else { 0 };
-
+pub fn storeb<F: PrimeField32>(rs2: usize, rs1: usize, imm: u32) -> Instruction<F> {
     Instruction::new(
         LoadStoreOpcode::STOREB.global_opcode(),
         F::from_canonical_usize(riscv::RV32_REGISTER_NUM_LIMBS * rs2), // a: rs2 (data to store)
         F::from_canonical_usize(riscv::RV32_REGISTER_NUM_LIMBS * rs1), // b: rs1 (base address)
-        F::from_canonical_usize(imm_unsigned),                         // c: imm (offset)
+        F::from_canonical_u32(imm & 0xFFFF),                           // c: imm (lower 16 bits)
         F::ONE,                                                        // d: register address space
-        F::from_canonical_usize(2), // e: memory address space (2 for byte, same as word)
+        F::from_canonical_usize(2), // e: memory address space (2 for byte)
         F::ONE,                     // f: enabled
-        F::from_canonical_usize(imm_sign), // g: imm sign
+        F::from_canonical_u32(imm >> 16), // g: imm (higher 16 bits)
     )
 }
 
 /// STOREH instruction: Store halfword to memory
 /// MEM[rs1 + imm] = rs2 (lowest halfword)
-pub fn storeh<F: PrimeField32>(rs2: usize, rs1: usize, imm: i32) -> Instruction<F> {
-    let imm_unsigned = (imm & 0xFFFFFF) as usize;
-    let imm_sign = if imm < 0 { 1 } else { 0 };
-
+pub fn storeh<F: PrimeField32>(rs2: usize, rs1: usize, imm: u32) -> Instruction<F> {
     Instruction::new(
         LoadStoreOpcode::STOREH.global_opcode(),
         F::from_canonical_usize(riscv::RV32_REGISTER_NUM_LIMBS * rs2), // a: rs2 (data to store)
         F::from_canonical_usize(riscv::RV32_REGISTER_NUM_LIMBS * rs1), // b: rs1 (base address)
-        F::from_canonical_usize(imm_unsigned),                         // c: imm (offset)
+        F::from_canonical_u32(imm & 0xFFFF),                           // c: imm (lower 16 bits)
         F::ONE,                                                        // d: register address space
-        F::from_canonical_usize(2), // e: memory address space (2 for halfword, same as word)
+        F::from_canonical_usize(2), // e: memory address space (2 for halfword)
         F::ONE,                     // f: enabled
-        F::from_canonical_usize(imm_sign), // g: imm sign
+        F::from_canonical_u32(imm >> 16), // g: imm (higher 16 bits)
     )
 }
 
diff --git a/integration/src/main.rs b/integration/src/main.rs
@@ -2142,6 +2142,15 @@ mod wast_tests {
         run_single_wasm_test("../sample-programs/keccak.wasm", "main", &[0, 0], &[]).unwrap()
     }
 
+    #[test]
+    fn test_keeper_js() {
+        // This is program is a stripped down version of geth, compiled for Go's js target.
+        // Source: https://github.com/ethereum/go-ethereum/tree/master/cmd/keeper
+        // Compile command:
+        //   GOOS=js GOARCH=wasm go -gcflags=all=-d=softfloat build -tags "example" -o keeper.wasm
+        run_single_wasm_test("../sample-programs/keeper_js.wasm", "run", &[0, 0], &[]).unwrap();
+    }
+
     #[test]
     fn test_keccak_rust_womir() {
         run_womir_guest(
diff --git a/integration/src/womir_translation.rs b/integration/src/womir_translation.rs
@@ -54,6 +54,11 @@ pub const ERROR_CODE_OFFSET: u32 = 100;
 
 pub const ERROR_ABORT_CODE: u32 = 200;
 
+/// Error code emitted in place of unimplemented instructions.
+/// This is to allow programs that has such instruction to compile,
+/// but the runtime error only happens if they are actually executed.
+pub const ERROR_UNIMPLEMENTED_CODE: u32 = 201;
+
 pub struct LinkedProgram<'a, F: PrimeField32> {
     module: Module<'a>,
     label_map: HashMap<String, LabelValue>,
@@ -644,6 +649,10 @@ impl<'a, F: PrimeField32> Settings<'a> for OpenVMSettings<F> {
             ("env", "abort") => {
                 vec![Directive::Instruction(ib::abort())]
             }
+            ("gojs", _) => {
+                // Just NOP for GoJS intrinsics
+                vec![]
+            }
             _ => unimplemented!(
                 "Imported function `{}` from module `{}` is not supported",
                 function,
@@ -1174,6 +1183,8 @@ fn translate_complex_ins<F: PrimeField32>(
         })
         .collect_vec();
     match op {
+        Op::Nop => Tree::Empty,
+
         Op::I32Const { value } => {
             let output = output.unwrap().start as usize;
             let value_u = value as u32;
@@ -1874,10 +1885,6 @@ fn translate_complex_ins<F: PrimeField32>(
         }
 
         // Float instructions
-        Op::F32Load { memarg: _ } => todo!(),
-        Op::F64Load { memarg: _ } => todo!(),
-        Op::F32Store { memarg: _ } => todo!(),
-        Op::F64Store { memarg: _ } => todo!(),
         Op::F32Const { value } => {
             let output = output.unwrap().start as usize;
             let value_u = value.bits();
@@ -1900,38 +1907,44 @@ fn translate_complex_ins<F: PrimeField32>(
             ]
             .into()
         }
-        Op::F32Abs => todo!(),
-        Op::F32Neg => todo!(),
-        Op::F32Ceil => todo!(),
-        Op::F32Floor => todo!(),
-        Op::F32Trunc => todo!(),
-        Op::F32Nearest => todo!(),
-        Op::F32Sqrt => todo!(),
-        Op::F64Abs => todo!(),
-        Op::F64Neg => todo!(),
-        Op::F64Ceil => todo!(),
-        Op::F64Floor => todo!(),
-        Op::F64Trunc => todo!(),
-        Op::F64Nearest => todo!(),
-        Op::F64Sqrt => todo!(),
-        Op::I32TruncF32S => todo!(),
-        Op::I32TruncF32U => todo!(),
-        Op::I32TruncF64S => todo!(),
-        Op::I32TruncF64U => todo!(),
-        Op::I64TruncF32S => todo!(),
-        Op::I64TruncF32U => todo!(),
-        Op::I64TruncF64S => todo!(),
-        Op::I64TruncF64U => todo!(),
-        Op::F32ConvertI32S => todo!(),
-        Op::F32ConvertI32U => todo!(),
-        Op::F32ConvertI64S => todo!(),
-        Op::F32ConvertI64U => todo!(),
-        Op::F32DemoteF64 => todo!(),
-        Op::F64ConvertI32S => todo!(),
-        Op::F64ConvertI32U => todo!(),
-        Op::F64ConvertI64S => todo!(),
-        Op::F64ConvertI64U => todo!(),
-        Op::F64PromoteF32 => todo!(),
+        Op::F32Load { .. }
+        | Op::F64Load { .. }
+        | Op::F32Store { .. }
+        | Op::F64Store { .. }
+        | Op::F32Abs
+        | Op::F32Neg
+        | Op::F32Ceil
+        | Op::F32Floor
+        | Op::F32Trunc
+        | Op::F32Nearest
+        | Op::F32Sqrt
+        | Op::F64Abs
+        | Op::F64Neg
+        | Op::F64Ceil
+        | Op::F64Floor
+        | Op::F64Trunc
+        | Op::F64Nearest
+        | Op::F64Sqrt
+        | Op::I32TruncF32S
+        | Op::I32TruncF32U
+        | Op::I32TruncF64S
+        | Op::I32TruncF64U
+        | Op::I64TruncF32S
+        | Op::I64TruncF32U
+        | Op::I64TruncF64S
+        | Op::I64TruncF64U
+        | Op::F32ConvertI32S
+        | Op::F32ConvertI32U
+        | Op::F32ConvertI64S
+        | Op::F32ConvertI64U
+        | Op::F32DemoteF64
+        | Op::F64ConvertI32S
+        | Op::F64ConvertI32U
+        | Op::F64ConvertI64S
+        | Op::F64ConvertI64U
+        | Op::F64PromoteF32 => {
+            Directive::Instruction(ib::trap(ERROR_UNIMPLEMENTED_CODE as usize)).into()
+        }
 
         Op::I32ReinterpretF32
         | Op::F32ReinterpretI32
@@ -1998,7 +2011,7 @@ fn emit_table_get<F: PrimeField32>(
         Directive::Instruction(ib::loadw(
             dest_reg as usize,
             mul_result,
-            base_addr as i32 + (i as i32) * 4,
+            base_addr + (i as u32) * 4,
         ))
     }));
 
@@ -2197,16 +2210,13 @@ fn const_i16_as_field(value: &WasmValue) -> AluImm {
     c.into()
 }
 
-fn mem_offset<F: PrimeField32>(memarg: MemArg, c: &Ctx<F>) -> i32 {
+fn mem_offset<F: PrimeField32>(memarg: MemArg, c: &Ctx<F>) -> u32 {
     assert_eq!(memarg.memory, 0, "no multiple memories supported");
     let mem_start = c
         .program
         .linear_memory_start()
         .expect("no memory allocated");
-    let offset = mem_start + u32::try_from(memarg.offset).expect("offset too large");
-    // RISC-V requires offset immediates to have 16 bits, but for WASM we changed it to 24 bits.
-    assert!(offset < (1 << 24));
-    offset as i32
+    mem_start.wrapping_add(u32::try_from(memarg.offset).expect("offset too large"))
 }
 
 fn load_from_const_addr<F: PrimeField32>(
@@ -2225,7 +2235,7 @@ fn load_from_const_addr<F: PrimeField32>(
         Directive::Instruction(ib::loadw(
             dest_reg as usize,
             base_addr_reg.start as usize,
-            (i as i32) * 4,
+            (i as u32) * 4,
         ))
     }));
 
@@ -2248,7 +2258,7 @@ fn store_to_const_addr<F: PrimeField32>(
         Directive::Instruction(ib::storew(
             input_reg as usize,
             base_addr_reg.start as usize,
-            i as i32 * 4,
+            i as u32 * 4,
         ))
     }));
 
diff --git a/sample-programs/keeper_js.wasm b/sample-programs/keeper_js.wasm
