[Bump hw dep] Remove soc910_pkg, update pulp-c910 dep, switch its source to github.

Author: Aquaticfuller

Bender.lock

@@ -152,10 +152,10 @@ packages:
     - register_interface
     - tech_cells_generic
   pulp_c910:
-    revision: 695b59aec93bfac9765db20528bdd0b47aa55650
+    revision: 6341db3bd41d372a471d16631b478d86a44eda75
     version: null
     source:
-      Git: [email protected]:nwistoff/pulp_c910.git
+      Git: https://github.com/pulp-platform/pulp-c910.git
     dependencies:
     - ace
     - apb

Bender.yml

@@ -30,7 +30,7 @@ dependencies:
   riscv-dbg:                { git: "https://github.com/pulp-platform/riscv-dbg.git",              rev: f69f6342   } # zx/cheshire_c910
   serial_link:              { git: "https://github.com/pulp-platform/serial_link.git",            version: 1.1.0  }
   unbent:                   { git: "https://github.com/pulp-platform/unbent.git",                 version: 0.1.5  }
-  pulp_c910:                { git: "[email protected]:nwistoff/pulp_c910.git",               rev: 695b59ae   } # dev_zx_cheshire_c910
+  pulp_c910:                { git: "https://github.com/pulp-platform/pulp-c910.git",              rev: 6341db3b   } # dev_zx_cheshire_c910
 
 export_include_dirs:
   - hw/include

hw/cheshire_pkg.sv

@@ -628,13 +628,16 @@ package cheshire_pkg;
 
 `ifdef TARGET_C910
   // C910 config
+  localparam int unsigned C910AxiDataWidth = 128; // for C910 core axi, the data path is 128bit
   function automatic cheshire_cfg_t gen_cheshire_c910_cfg();
     cheshire_cfg_t ret  = DefaultCfg;
     ret.Core            = C910;
-    ret.AddrWidth       = soc910_pkg::AxiAddrWidth;
-    ret.AxiMaxMstTrans  = soc910_pkg::AxiMaxMstTrans;
-    ret.AxiMstIdWidth   = soc910_pkg::AxiIdWidthMaster;
-    ret.AxiUserWidth    = soc910_pkg::AxiUserWidth;
+    ret.AddrWidth       = 40;
+    ret.AxiDataWidth    = 64; // for SoC, the data path remain 64bit
+    // 8n(Non-cacheable/Device) + 28(cacheable) read + 8n(Non-cacheable/Device) + 32(cacheable) write
+    ret.AxiMaxMstTrans  = 76;
+    ret.AxiMstIdWidth   = 8;
+    ret.AxiUserWidth    = 2;
     return ret;
   endfunction
 `endif

hw/cheshire_soc.sv

@@ -577,11 +577,11 @@ module cheshire_soc import cheshire_pkg::*; #(
                             axi_user_t)
   // 128-bit axi master
   `CHESHIRE_TYPEDEF_AXI_CT( axi_c910,
-                          addr_t,
-                          logic[soc910_pkg::AxiIdWidthMaster-1:0],
-                          logic[soc910_pkg::AxiDataWidth-1:0],
-                          logic[soc910_pkg::AxiDataWidth/8-1:0],
-                          logic[soc910_pkg::AxiUserWidth-1:0]
+                            addr_t,
+                            logic[Cfg.AxiMstIdWidth-1:0],
+                            logic[C910AxiDataWidth-1:0],
+                            logic[C910AxiDataWidth/8-1:0],
+                            logic[Cfg.AxiUserWidth-1:0]
                           )
 `endif
 
@@ -670,12 +670,12 @@ module cheshire_soc import cheshire_pkg::*; #(
       c910_axi_wrap #(
         .AxiSetModifiable ( 1'b1              ),
         .AxiUnwrapBursts  ( 1'b1              ),
-        .AddrWidth        ( soc910_pkg::AxiAddrWidth    ),
-        .DataWidth        ( soc910_pkg::AxiDataWidth    ),
-        .IdWidth          ( soc910_pkg::AxiIdWidthMaster),
-        .UserWidth        ( soc910_pkg::AxiUserWidth    ),
-        .axi_req_t        ( axi_c910_req_t ),
-        .axi_rsp_t        ( axi_c910_rsp_t )
+        .AddrWidth        ( Cfg.AddrWidth     ),
+        .DataWidth        ( C910AxiDataWidth  ),
+        .IdWidth          ( Cfg.AxiMstIdWidth ),
+        .UserWidth        ( Cfg.AxiUserWidth  ),
+        .axi_req_t        ( axi_c910_req_t    ),
+        .axi_rsp_t        ( axi_c910_rsp_t    )
       ) i_c910_axi_wrap (
         .clk_i,
         .rst_ni,
@@ -750,7 +750,7 @@ module cheshire_soc import cheshire_pkg::*; #(
 
       axi_dw_converter #(
         .AxiMaxReads         ( 8                      ), // Number of outstanding reads
-        .AxiSlvPortDataWidth ( soc910_pkg::AxiDataWidth), // Data width of the slv port
+        .AxiSlvPortDataWidth ( C910AxiDataWidth       ), // Data width of the slv port
         .AxiMstPortDataWidth ( Cfg.AxiDataWidth       ), // Data width of the mst port
         .AxiAddrWidth        ( Cfg.AddrWidth          ), // Address width
         .AxiIdWidth          ( Cfg.AxiMstIdWidth      ), // ID width
@@ -818,11 +818,11 @@ module cheshire_soc import cheshire_pkg::*; #(
         );
       end else begin: gen_i_c910_bus_err
           axi_err_unit_wrap #(
-          .AddrWidth          ( Cfg.AddrWidth ),
-          .IdWidth            ( soc910_pkg::AxiIdWidthMaster   ),
-          .UserErrBits        ( Cfg.AxiUserErrBits ),
-          .UserErrBitsOffset  ( Cfg.AxiUserErrLsb ),
-          .NumOutstanding     ( Cfg.CoreMaxTxns ),
+          .AddrWidth          ( Cfg.AddrWidth       ),
+          .IdWidth            ( Cfg.AxiMstIdWidth   ),
+          .UserErrBits        ( Cfg.AxiUserErrBits  ),
+          .UserErrBitsOffset  ( Cfg.AxiUserErrLsb   ),
+          .NumOutstanding     ( Cfg.CoreMaxTxns     ),
           .NumStoredErrors    ( 4 ),
           .DropOldest         ( 1'b0 ),
           .axi_req_t          ( axi_cva6_req_t ),

target/xilinx/src/cheshire_top_xilinx.sv

@@ -189,10 +189,12 @@ module cheshire_top_xilinx
     cheshire_cfg_t ret  = FPGACfg;
 `ifdef TARGET_C910
     ret.Core            = C910;
-    ret.AddrWidth       = soc910_pkg::AxiAddrWidth;
-    ret.AxiMaxMstTrans  = soc910_pkg::AxiMaxMstTrans;
-    ret.AxiMstIdWidth   = soc910_pkg::AxiIdWidthMaster;
-    ret.AxiUserWidth    = soc910_pkg::AxiUserWidth;
+    ret.AddrWidth       = 40;
+    ret.AxiDataWidth    = 64; // for SoC, the data path remain 64bit
+    // 8n(Non-cacheable/Device) + 28(cacheable) read + 8n(Non-cacheable/Device) + 32(cacheable) write
+    ret.AxiMaxMstTrans  = 76;
+    ret.AxiMstIdWidth   = 8;
+    ret.AxiUserWidth    = 2;
 `endif
     return ret;
   endfunction