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Commit 9e08280

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Lint fixes
1 parent c326a3b commit 9e08280

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2 files changed

+26
-35
lines changed

2 files changed

+26
-35
lines changed

sw/lib/smp.c

Lines changed: 18 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -11,41 +11,38 @@ void smp_resume(void) {
1111
uint32_t num_harts = *reg32(&__base_regs, CHESHIRE_NUM_INT_HARTS_REG_OFFSET);
1212
// Flush cache and wake-up all sleeping cores
1313
fence();
14-
for (uint32_t i=1; i<num_harts; i++) {
14+
for (uint32_t i = 1; i < num_harts; i++) {
1515
*reg32(&__base_clint, i << 2) = 0x1;
16-
while (*reg32(&__base_clint, i << 2));
16+
while (*reg32(&__base_clint, i << 2))
17+
;
1718
}
1819
}
1920

2021
// Shared variable for barrier synchronization
2122
static volatile uint64_t _barrier_target = 0;
2223

23-
static void barrier_wait(volatile uint64_t* barrier, uint64_t incr, uint64_t reach) {
24-
asm volatile (
25-
"amoadd.d x6, %1, (%0) \n"
26-
"2: \n"
27-
"fence \n"
28-
"ld x6, 0(%0) \n"
29-
"bne x6, %2, 2b \n"
30-
31-
: /* output operands */
32-
: /* input operands */
33-
"r"(barrier),
34-
"r"(incr),
35-
"r"(reach)
36-
: /* clobbered registers */
37-
"x6"
38-
);
24+
static void barrier_wait(volatile uint64_t *barrier, uint64_t incr, uint64_t reach) {
25+
asm volatile("amoadd.d x6, %1, (%0) \n"
26+
"2: \n"
27+
"fence \n"
28+
"ld x6, 0(%0) \n"
29+
"bne x6, %2, 2b \n"
30+
31+
: /* output operands */
32+
: /* input operands */
33+
"r"(barrier), "r"(incr), "r"(reach)
34+
: /* clobbered registers */
35+
"x6");
3936
}
4037

4138
void smp_barrier_init() {
42-
_barrier_target = 0;
39+
_barrier_target = 0;
4340
}
4441

4542
void smp_barrier_up(uint64_t n_processes) {
46-
barrier_wait(&_barrier_target, 1, n_processes);
43+
barrier_wait(&_barrier_target, 1, n_processes);
4744
}
4845

4946
void smp_barrier_down() {
50-
barrier_wait(&_barrier_target, -1, 0);
47+
barrier_wait(&_barrier_target, -1, 0);
5148
}

sw/tests/smp_hello.c

Lines changed: 8 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -20,29 +20,23 @@
2020
uint32_t __attribute__((section(".data"))) semaphore = 0x0;
2121

2222
void semaphore_wait() {
23-
asm volatile (
24-
" li t0, 1 \n"
25-
"1: \n"
26-
" amoswap.w.aq t0, t0, (%0) \n"
27-
" bnez t0, 1b \n"
28-
::"r"(&semaphore)
29-
);
23+
asm volatile(" li t0, 1 \n"
24+
"1: \n"
25+
" amoswap.w.aq t0, t0, (%0) \n"
26+
" bnez t0, 1b \n" ::"r"(&semaphore));
3027
}
3128

3229
void semaphore_post() {
33-
asm volatile (
34-
" amoswap.w.rl zero, zero, (%0) \n"
35-
::"r"(&semaphore)
36-
);
30+
asm volatile(" amoswap.w.rl zero, zero, (%0) \n" ::"r"(&semaphore));
3731
}
3832

3933
int main(void) {
4034

41-
uint64_t hart_id = get_mhartid();
35+
uint64_t hart_id = get_mhartid();
4236
uint32_t num_harts = *reg32(&__base_regs, CHESHIRE_NUM_INT_HARTS_REG_OFFSET);
4337

4438
if (hart_id == 0) {
45-
uint32_t rtc_freq = *reg32(&__base_regs, CHESHIRE_RTC_FREQ_REG_OFFSET);
39+
uint32_t rtc_freq = *reg32(&__base_regs, CHESHIRE_RTC_FREQ_REG_OFFSET);
4640
uint64_t reset_freq = clint_get_core_freq(rtc_freq, 2500);
4741
uart_init(&__base_uart, reset_freq, __BOOT_BAUDRATE);
4842
smp_barrier_init();
@@ -51,7 +45,7 @@ int main(void) {
5145

5246
smp_barrier_up(num_harts);
5347

54-
for (uint64_t i=0; i<1; i++) {
48+
for (uint64_t i = 0; i < 1; i++) {
5549
semaphore_wait();
5650
printf("Core %d/%d up\n", hart_id, num_harts);
5751
uart_write_flush(&__base_uart);

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