@@ -11,41 +11,38 @@ void smp_resume(void) {
1111 uint32_t num_harts = * reg32 (& __base_regs , CHESHIRE_NUM_INT_HARTS_REG_OFFSET );
1212 // Flush cache and wake-up all sleeping cores
1313 fence ();
14- for (uint32_t i = 1 ; i < num_harts ; i ++ ) {
14+ for (uint32_t i = 1 ; i < num_harts ; i ++ ) {
1515 * reg32 (& __base_clint , i << 2 ) = 0x1 ;
16- while (* reg32 (& __base_clint , i << 2 ));
16+ while (* reg32 (& __base_clint , i << 2 ))
17+ ;
1718 }
1819}
1920
2021// Shared variable for barrier synchronization
2122static volatile uint64_t _barrier_target = 0 ;
2223
23- static void barrier_wait (volatile uint64_t * barrier , uint64_t incr , uint64_t reach ) {
24- asm volatile (
25- "amoadd.d x6, %1, (%0) \n"
26- "2: \n"
27- "fence \n"
28- "ld x6, 0(%0) \n"
29- "bne x6, %2, 2b \n"
30-
31- : /* output operands */
32- : /* input operands */
33- "r" (barrier ),
34- "r" (incr ),
35- "r" (reach )
36- : /* clobbered registers */
37- "x6"
38- );
24+ static void barrier_wait (volatile uint64_t * barrier , uint64_t incr , uint64_t reach ) {
25+ asm volatile ("amoadd.d x6, %1, (%0) \n"
26+ "2: \n"
27+ "fence \n"
28+ "ld x6, 0(%0) \n"
29+ "bne x6, %2, 2b \n"
30+
31+ : /* output operands */
32+ : /* input operands */
33+ "r" (barrier ), "r" (incr ), "r" (reach )
34+ : /* clobbered registers */
35+ "x6" );
3936}
4037
4138void smp_barrier_init () {
42- _barrier_target = 0 ;
39+ _barrier_target = 0 ;
4340}
4441
4542void smp_barrier_up (uint64_t n_processes ) {
46- barrier_wait (& _barrier_target , 1 , n_processes );
43+ barrier_wait (& _barrier_target , 1 , n_processes );
4744}
4845
4946void smp_barrier_down () {
50- barrier_wait (& _barrier_target , -1 , 0 );
47+ barrier_wait (& _barrier_target , -1 , 0 );
5148}
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