From 994bef72c0c3f60a43a44bf96abb5b8141444b2e Mon Sep 17 00:00:00 2001 From: Cyril Koenig Date: Sun, 5 Jan 2025 14:40:19 +0100 Subject: [PATCH 1/3] pkg: Add LLC bypass memory region at 0x20000000 --- hw/cheshire_pkg.sv | 6 ++++++ target/xilinx/src/cheshire_top_xilinx.sv | 2 ++ 2 files changed, 8 insertions(+) diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv index b99fec6b0..8e607d6cb 100644 --- a/hw/cheshire_pkg.sv +++ b/hw/cheshire_pkg.sv @@ -162,6 +162,8 @@ package cheshire_pkg; bit LlcOutConnect; doub_bt LlcOutRegionStart; doub_bt LlcOutRegionEnd; + doub_bt LlcBypassRegionStart; + doub_bt LlcBypassRegionEnd; dw_bt LlcUserMsb; dw_bt LlcUserLsb; // Parameters for VGA @@ -348,6 +350,8 @@ package cheshire_pkg; // own Xbar output with the specified region iff it is connected. if (cfg.LlcOutConnect) begin i++; r++; ret.llc = i; ret.map[r] = '{i, cfg.LlcOutRegionStart, cfg.LlcOutRegionEnd}; end + if (cfg.LlcOutConnect) begin r++; + ret.map[r] = '{i, cfg.LlcBypassRegionStart, cfg.LlcBypassRegionEnd}; end // We can only internally map the SPM region if an LLC exists. // Otherwise, we assume external ports map and back the SPM region. // We map both the cached and uncached regions. @@ -589,6 +593,8 @@ package cheshire_pkg; LlcOutConnect : 1, LlcOutRegionStart : 'h8000_0000, LlcOutRegionEnd : 'h1_0000_0000, + LlcBypassRegionStart : 'h2_8000_0000, + LlcBypassRegionEnd : 'h3_0000_0000, LlcUserMsb : 0, LlcUserLsb : 0, // LLC Partitioning diff --git a/target/xilinx/src/cheshire_top_xilinx.sv b/target/xilinx/src/cheshire_top_xilinx.sv index ae1786f72..d05fc6992 100644 --- a/target/xilinx/src/cheshire_top_xilinx.sv +++ b/target/xilinx/src/cheshire_top_xilinx.sv @@ -123,6 +123,8 @@ module cheshire_top_xilinx LlcOutConnect : 1, LlcOutRegionStart : 'h8000_0000, LlcOutRegionEnd : 'h1_0000_0000, + LlcBypassRegionStart : 'h2_8000_0000, + LlcBypassRegionEnd : 'h3_0000_0000, LlcUserMsb : 0, LlcUserLsb : 0, // LLC partitioning From 04c05a80a778f49c02146a54c165d94c44b02c71 Mon Sep 17 00:00:00 2001 From: Cyril Koenig Date: Sun, 5 Jan 2025 15:46:59 +0100 Subject: [PATCH 2/3] bender: Update axi_llc with SPM debug --- Bender.lock | 2 +- Bender.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Bender.lock b/Bender.lock index 9b07ef1d3..6e814e125 100644 --- a/Bender.lock +++ b/Bender.lock @@ -24,7 +24,7 @@ packages: - common_verification - tech_cells_generic axi_llc: - revision: 7d7fc1349d4915a657de535a491bc26fbf0d2cfa + revision: 7c681312ae1eb912052de98ddaf5d19e1c2b76ff version: null source: Git: https://github.com/pulp-platform/axi_llc.git diff --git a/Bender.yml b/Bender.yml index 43a7f865c..b5ba6bcc2 100644 --- a/Bender.yml +++ b/Bender.yml @@ -14,7 +14,7 @@ package: dependencies: apb_uart: { git: "https://github.com/pulp-platform/apb_uart.git", version: 0.2.1 } axi: { git: "https://github.com/pulp-platform/axi", rev: 4fb5a02 } - axi_llc: { git: "https://github.com/pulp-platform/axi_llc", rev: 7d7fc13 } + axi_llc: { git: "https://github.com/pulp-platform/axi_llc", rev: 7c68131 } # branch: llc_partition_opt axi_riscv_atomics: { git: "https://github.com/pulp-platform/axi_riscv_atomics.git", version: 0.8.1 } axi_rt: { git: "https://github.com/pulp-platform/axi_rt.git", version: 0.0.0-alpha.4 } axi_vga: { git: "https://github.com/pulp-platform/axi_vga.git", version: 0.1.1 } From 0071e68fdca331a81e9467ea11be222fefeae4cc Mon Sep 17 00:00:00 2001 From: Cyril Koenig Date: Sun, 5 Jan 2025 16:13:13 +0100 Subject: [PATCH 3/3] sw: Add LLC functions --- sw/include/dif/axi_llc.h | 13 +++++++++++++ sw/lib/dif/llc.c | 38 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+) create mode 100644 sw/include/dif/axi_llc.h create mode 100644 sw/lib/dif/llc.c diff --git a/sw/include/dif/axi_llc.h b/sw/include/dif/axi_llc.h new file mode 100644 index 000000000..c45f24889 --- /dev/null +++ b/sw/include/dif/axi_llc.h @@ -0,0 +1,13 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Cyril Koenig + +#pragma once + +void llc_enable(); + +void llc_flush(); + +void llc_disable(); diff --git a/sw/lib/dif/llc.c b/sw/lib/dif/llc.c new file mode 100644 index 000000000..827437b6c --- /dev/null +++ b/sw/lib/dif/llc.c @@ -0,0 +1,38 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Cyril Koenig + +#include "dif/axi_llc.h" +#include "regs/axi_llc.h" +#include "util.h" +#include "params.h" + +void llc_enable() { + *reg32(&__base_llc, AXI_LLC_CFG_SPM_LOW_REG_OFFSET ) = 0x00000000; + *reg32(&__base_llc, AXI_LLC_CFG_SPM_HIGH_REG_OFFSET) = 0x00000000; + fence(); + *reg32(&__base_llc, AXI_LLC_COMMIT_CFG_REG_OFFSET) = 0x1; + fence(); +} + +void llc_flush() { + *reg32(&__base_llc, AXI_LLC_CFG_FLUSH_LOW_REG_OFFSET ) = 0xffffffff; + *reg32(&__base_llc, AXI_LLC_CFG_FLUSH_HIGH_REG_OFFSET) = 0xffffffff; + fence(); + *reg32(&__base_llc, AXI_LLC_COMMIT_CFG_REG_OFFSET) = 0x1; + fence(); + while(*reg32(&__base_llc, AXI_LLC_CFG_FLUSH_LOW_REG_OFFSET) != 0); + while(*reg32(&__base_llc, AXI_LLC_CFG_FLUSH_HIGH_REG_OFFSET) != 0); +} + +void llc_disable() { + *reg32(&__base_llc, AXI_LLC_CFG_SPM_LOW_REG_OFFSET ) = 0xffffffff; + *reg32(&__base_llc, AXI_LLC_CFG_SPM_HIGH_REG_OFFSET) = 0xffffffff; + *reg32(&__base_llc, AXI_LLC_CFG_FLUSH_LOW_REG_OFFSET ) = 0xffffffff; + *reg32(&__base_llc, AXI_LLC_CFG_FLUSH_HIGH_REG_OFFSET) = 0xffffffff; + fence(); + *reg32(&__base_llc, AXI_LLC_COMMIT_CFG_REG_OFFSET) = 0x1; + fence(); +}