WIP: zx/c910 preopen #190
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WIP: zx/c910 preopen #190
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…d Vivado IP simulation flow fpga: Added ddr4 and vcu128 flow, added draft of Vivado IP simulation flow fpga: Added VIOs Connect VIO-generated reset signal to dram wrapper fpga: Support of zcu102 fpga: zcu102.xdc constraint file added fpga: zcu102 changed phy and added firsts constraints fpga: Switching to clk_wiz and xilinx.mk fpga: Testing ddr4 fpga: Start working on SPI driver Co-Authored-By: Yann Picod <[email protected]> fpga: SD card test fpga: Rolled-back SD fpga: Add vcu128 ci fpga: Debug new CI fpga: Adding artifacts management fpga: Added ID serializer in dram_wrapper and changed a few xdc constraints fpga: Correcting artifacts mngmt and applied new constraints to genesys2 fpga: Corrected vivado sim script fpga: Last review updates fpga: Last review updates 2 fpga: Updated artifact management to take select only useful envvar fpga: Update cva6-sdk, add openocd configs, and update docs fpga: Use https for cva6-sdk
…om boot rom, but it jump back to addr 0 again
…orrect order of return data from reg to axi
…eshire's original bootrom didn't reset all registers(e.g. x2, x3), may cause c910 renaming unit bug; 3. After fix 2 by completing all register resets in bootrom, find a lsu exception, which caused by accessing to Cheshire's config reg, still to be fixed
…’s top, to propagate the misp and mtip interrupt signals from CLINT to the core. 2.added the axi_dw_converter to convert c910 128-bit width AXI to Cheshire 64-bit width AXI interface, now it can run baremetal helloworld.spm.elf program completely
…i signal in i_llc_config_regfile need to be set to 0 or it will cause a error for accessing unmapped register
…rom bootrom to memory address; 2. update dependency pulp_c910
…mplementation timing constraint
1.add cheshire_reg_t class to simulate cheshire_reg soc configuration registers.
2.add csr load & store support: pmpaddr, pmpcfg, mhpmcounter, mhpmevent, mcountinhibit.
3.add csr time, which is a read-only copy of mtime, when access it, it would read mtime in clint from system bus.
4.add counter and uart_tick function in uart_t to simulate the tx state machine.
5.the c910 core has following retire mechanism:
1) 1 retire can fold at most 3 instructions, the retire address is the address of the head folded instruction;
2) the recover renaming table update can be cycles later than the retire, even comes later than the next retire.
as a result, in spike.cc, use following methods to co-sim:
1) when a retire_valid comes, tick spike to the retire address, and compare the aregs and csrs with spike info from the last tick(to find to end inst of last retire);
2) if spike ticks SpikeRunAheadInstMax time bus still can't reach a pc matches the retire addres, consider a pc mismatch and call $stop;
3) if areg and csr mismatch, only print warning, don't stop; if privilege level mismatch, call $stop;
6. to match the opensbi uart tx print, set the main clk: ClkPeriodSys to 20ns(50MHz).
7. find occasionally the c910 core can send axi ar request to address 0, where is the memory region of debug module, and if that ar req doesn't get a r resp, it can stall the core, so add the cheshire debug module back, for now only to handle the ar req.
Now the rtl-spike co-sim can run opensbi with directly load the elf into dram, there is still some problem with the sbi_domain & pmp setting, may because the fdt isn't correctly passed to opensbi.
…errupt bug. 2.Add trc port to c910 core. 3.Add 2 more preload binary files for simulation, to load fw_payload(opensbi+uboot), vmlinux, dtb resoectively.
…ware features. Add a ace_dummy_handler to handle ace req that needs a b resp
…ly set core frequency to 50MHz instead of let it detect, or it would stuck at asl firmware loading stage, need to look into it.
…hile the ar haven't sent out and the rb_entry_biu_id hasn't get updated.
…ke sure only the not_full signal from the data entry with the same r id with the incoming r can affect the output ready signal.
1.Update pulp_c910 dep, add risc-v debug support. 2.Update riscv-dbg dep, to make it compatible with c910. 3.Update axi dep, fix the axi unwrap module issue.
…he THead defined CSR MCOR to be both M & S mode readable/writable, for cache inv/clr in S mode.
…dy is low, don't increase the axi_burst_counter, or the unhandshaked AR will be lost.
1. Add ar transaction handling in the ace_dummy_handler module; 2. Increase LFB buffer capacity to prevent core deadlock in heavy memory transactions.
1. Several issues in Makefiles; 2. Bump the c910-sdk dep.
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…d to dedicate a SoC memory range for the c910 snoop evict request response. 2. Update dependencies
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Merge the c910 supports to the main branch.