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hw: Integrate PULP Cluster in chimera_cluster and config
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4 files changed

+293
-20
lines changed

4 files changed

+293
-20
lines changed

‎hw/chimera_clu_domain.sv‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -176,6 +176,7 @@ module chimera_clu_domain
176176
chimera_cluster #(
177177
.Cfg (Cfg),
178178
.NrCores (`NRCORES(extClusterIdx)),
179+
.ClusterId (extClusterIdx),
179180
.narrow_in_req_t (narrow_in_req_t),
180181
.narrow_in_resp_t (narrow_in_resp_t),
181182
.narrow_out_req_t (narrow_out_req_t),

‎hw/chimera_cluster.sv‎

Lines changed: 193 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@ module chimera_cluster
1212
parameter chimera_cfg_t Cfg = '0,
1313

1414
parameter int unsigned NrCores = 9,
15+
parameter int unsigned ClusterId = 0,
1516
parameter type narrow_in_req_t = logic,
1617
parameter type narrow_in_resp_t = logic,
1718
parameter type narrow_out_req_t = logic,
@@ -51,6 +52,7 @@ module chimera_cluster
5152
);
5253

5354
`include "axi/typedef.svh"
55+
`include "axi/assign.svh"
5456

5557
localparam int WideDataWidth = $bits(wide_out_req_o.w.data);
5658

@@ -183,27 +185,35 @@ module chimera_cluster
183185

184186
) i_cluster_axi_adapter (
185187
.soc_clk_i(soc_clk_i),
188+
`ifndef TARGET_PULP_CLUSTER
186189
.clu_clk_i(clu_clk_i),
190+
`endif
187191
.rst_ni,
188192

189193
.narrow_in_req_i (clu_axi_narrow_slv_req),
190194
.narrow_in_resp_o (clu_axi_narrow_slv_rsp),
191195
.narrow_out_req_o (clu_axi_narrow_mst_req),
192196
.narrow_out_resp_i(clu_axi_narrow_mst_rsp),
193197

194-
.clu_narrow_in_req_o (clu_axi_adapter_slv_req),
198+
.clu_narrow_in_req_o (clu_axi_adapter_slv_req), // Cluster side narrow slave
195199
.clu_narrow_in_resp_i (clu_axi_adapter_slv_resp),
196-
.clu_narrow_out_req_i (clu_axi_adapter_mst_req),
200+
.clu_narrow_out_req_i (clu_axi_adapter_mst_req), // Cluster side narrow master
197201
.clu_narrow_out_resp_o(clu_axi_adapter_mst_resp),
198202

199203
.wide_out_req_o (wide_out_req_o),
200204
.wide_out_resp_i (wide_out_resp_i),
201-
.clu_wide_out_req_i (clu_axi_wide_mst_req),
205+
.clu_wide_out_req_i (clu_axi_wide_mst_req), // Cluster side wide master
202206
.clu_wide_out_resp_o(clu_axi_wide_mst_resp),
203207

204208
.wide_mem_bypass_mode_i(widemem_bypass_i)
205209
);
206210

211+
////////////////////
212+
// Snitch cluster //
213+
////////////////////
214+
215+
`ifdef TARGET_SNITCH_CLUSTER
216+
207217
typedef struct packed {
208218
logic [2:0] ema;
209219
logic [1:0] emaw;
@@ -292,6 +302,186 @@ module chimera_cluster
292302
.wide_in_resp_o (),
293303
.wide_out_req_o (clu_axi_wide_mst_req),
294304
.wide_out_resp_i (clu_axi_wide_mst_resp)
305+
);
295306

307+
//////////////////
308+
// PULP cluster //
309+
//////////////////
310+
311+
`elsif TARGET_PULP_CLUSTER
312+
313+
// SoC to Cluster CDC source slice (narrow slave)
314+
AXI_BUS #(
315+
.AXI_ADDR_WIDTH ( Cfg.ChsCfg.AddrWidth ),
316+
.AXI_DATA_WIDTH ( ClusterDataWidth ),
317+
.AXI_ID_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiIdInWidth ),
318+
.AXI_USER_WIDTH ( Cfg.ChsCfg.AxiUserWidth )
319+
) soc_to_cluster_axi_bus();
320+
AXI_BUS_ASYNC_GRAY #(
321+
.AXI_ADDR_WIDTH ( Cfg.ChsCfg.AddrWidth ),
322+
.AXI_DATA_WIDTH ( ClusterDataWidth ),
323+
.AXI_ID_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiIdInWidth ),
324+
.AXI_USER_WIDTH ( Cfg.ChsCfg.AxiUserWidth ),
325+
.LOG_DEPTH ( Cfg.PulpCluCfgs[ClusterId].AxiCdcLogDepth )
326+
) async_soc_to_cluster_axi_bus();
327+
328+
axi_cdc_src_intf #(
329+
.AXI_ADDR_WIDTH ( Cfg.ChsCfg.AddrWidth ),
330+
.AXI_DATA_WIDTH ( ClusterDataWidth ),
331+
.AXI_ID_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiIdInWidth ),
332+
.AXI_USER_WIDTH ( Cfg.ChsCfg.AxiUserWidth ),
333+
.LOG_DEPTH ( Cfg.PulpCluCfgs[ClusterId].AxiCdcLogDepth )
334+
) soc_to_cluster_src_cdc_fifo_i (
335+
.src_clk_i ( soc_clk_i ),
336+
.src_rst_ni ( rst_ni ),
337+
.src ( soc_to_cluster_axi_bus ),
338+
.dst ( async_soc_to_cluster_axi_bus )
296339
);
340+
341+
`AXI_ASSIGN_FROM_REQ(soc_to_cluster_axi_bus, clu_axi_adapter_slv_req)
342+
`AXI_ASSIGN_TO_RESP(clu_axi_adapter_slv_resp, soc_to_cluster_axi_bus)
343+
344+
// Cluster to SoC CDC destination slice (narrow master)
345+
AXI_BUS #(
346+
.AXI_ADDR_WIDTH ( Cfg.ChsCfg.AddrWidth ),
347+
.AXI_DATA_WIDTH ( ClusterDataWidth ),
348+
.AXI_ID_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiIdOutWidth ),
349+
.AXI_USER_WIDTH ( Cfg.ChsCfg.AxiUserWidth )
350+
) cluster_to_soc_axi_bus();
351+
AXI_BUS_ASYNC_GRAY #(
352+
.AXI_ADDR_WIDTH ( Cfg.ChsCfg.AddrWidth ),
353+
.AXI_DATA_WIDTH ( ClusterDataWidth ),
354+
.AXI_ID_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiIdOutWidth ),
355+
.AXI_USER_WIDTH ( Cfg.ChsCfg.AxiUserWidth ),
356+
.LOG_DEPTH ( Cfg.PulpCluCfgs[ClusterId].AxiCdcLogDepth )
357+
) async_cluster_to_soc_axi_bus();
358+
359+
axi_cdc_dst_intf #(
360+
.AXI_ADDR_WIDTH ( Cfg.ChsCfg.AddrWidth ),
361+
.AXI_DATA_WIDTH ( ClusterDataWidth ),
362+
.AXI_ID_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiIdOutWidth ),
363+
.AXI_USER_WIDTH ( Cfg.ChsCfg.AxiUserWidth ),
364+
.LOG_DEPTH ( Cfg.PulpCluCfgs[ClusterId].AxiCdcLogDepth )
365+
) cluster_to_soc_dst_cdc_fifo_i (
366+
.dst_clk_i ( soc_clk_i ),
367+
.dst_rst_ni ( rst_ni ),
368+
.src ( async_cluster_to_soc_axi_bus ),
369+
.dst ( cluster_to_soc_axi_bus )
370+
);
371+
372+
`AXI_ASSIGN_TO_REQ(clu_axi_adapter_mst_req, cluster_to_soc_axi_bus)
373+
`AXI_ASSIGN_FROM_RESP(cluster_to_soc_axi_bus, clu_axi_adapter_mst_resp)
374+
375+
// DMA CDC destination slice (wide master)
376+
AXI_BUS #(
377+
.AXI_ADDR_WIDTH ( Cfg.ChsCfg.AddrWidth ),
378+
.AXI_DATA_WIDTH ( WideDataWidth ),
379+
.AXI_ID_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiIdOutWideWidth ),
380+
.AXI_USER_WIDTH ( Cfg.ChsCfg.AxiUserWidth )
381+
) dma_axi_bus();
382+
AXI_BUS_ASYNC_GRAY #(
383+
.AXI_ADDR_WIDTH ( Cfg.ChsCfg.AddrWidth ),
384+
.AXI_DATA_WIDTH ( WideDataWidth ),
385+
.AXI_ID_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiIdOutWideWidth ),
386+
.AXI_USER_WIDTH ( Cfg.ChsCfg.AxiUserWidth ),
387+
.LOG_DEPTH ( Cfg.PulpCluCfgs[ClusterId].AxiCdcLogDepth )
388+
) async_dma_axi_bus();
389+
390+
axi_cdc_dst_intf #(
391+
.AXI_ADDR_WIDTH ( Cfg.ChsCfg.AddrWidth ),
392+
.AXI_DATA_WIDTH ( WideDataWidth ),
393+
.AXI_ID_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiIdOutWideWidth ),
394+
.AXI_USER_WIDTH ( Cfg.ChsCfg.AxiUserWidth ),
395+
.LOG_DEPTH ( Cfg.PulpCluCfgs[ClusterId].AxiCdcLogDepth )
396+
) dma_dst_cdc_fifo_i (
397+
.dst_clk_i ( soc_clk_i ),
398+
.dst_rst_ni ( rst_ni ),
399+
.src ( async_dma_axi_bus ),
400+
.dst ( dma_axi_bus )
401+
);
402+
403+
`AXI_ASSIGN_TO_REQ(clu_axi_wide_mst_req, dma_axi_bus)
404+
`AXI_ASSIGN_FROM_RESP(dma_axi_bus, clu_axi_wide_mst_resp)
405+
406+
pulp_cluster #(
407+
.Cfg ( Cfg.PulpCluCfgs[ClusterId] )
408+
) cluster_i (
409+
.clk_i ( clu_clk_i ),
410+
.rst_ni ( rst_ni ),
411+
.pwr_on_rst_ni ( rst_ni ),
412+
.ref_clk_i ( clu_clk_i ),
413+
.axi_isolate_i ( '0 ),
414+
.axi_isolated_o ( /* Unconnected */ ),
415+
.axi_isolated_wide_o ( /* Unconnected */ ),
416+
.pmu_mem_pwdn_i ( 1'b0 ),
417+
.base_addr_i ( Cfg.PulpCluCfgs[ClusterId].ClusterBaseAddr[31:28] ),
418+
.dma_pe_evt_ack_i ( '1 ),
419+
.dma_pe_evt_valid_o ( /* Unconnected */ ),
420+
.dma_pe_irq_ack_i ( 1'b1 ),
421+
.dma_pe_irq_valid_o ( /* Unconnected */ ),
422+
.dbg_irq_valid_i ( '0 ),
423+
.mbox_irq_i ( '0 ),
424+
.pf_evt_ack_i ( 1'b1 ),
425+
.pf_evt_valid_o ( /* Unconnected */ ),
426+
.async_cluster_events_wptr_i ( '0 ),
427+
.async_cluster_events_rptr_o ( /* Unconnected */ ),
428+
.async_cluster_events_data_i ( '0 ),
429+
.en_sa_boot_i ( 1'b0 ),
430+
.test_mode_i ( 1'b0 ),
431+
.fetch_en_i ( 1'b0 ),
432+
.eoc_o ( /* Unconnected */ ),
433+
.busy_o ( /* Unconnected */ ),
434+
.cluster_id_i ( ClusterId[5:0] ),
435+
.async_data_master_aw_wptr_o ( async_cluster_to_soc_axi_bus.aw_wptr ),
436+
.async_data_master_aw_rptr_i ( async_cluster_to_soc_axi_bus.aw_rptr ),
437+
.async_data_master_aw_data_o ( async_cluster_to_soc_axi_bus.aw_data ),
438+
.async_data_master_ar_wptr_o ( async_cluster_to_soc_axi_bus.ar_wptr ),
439+
.async_data_master_ar_rptr_i ( async_cluster_to_soc_axi_bus.ar_rptr ),
440+
.async_data_master_ar_data_o ( async_cluster_to_soc_axi_bus.ar_data ),
441+
.async_data_master_w_data_o ( async_cluster_to_soc_axi_bus.w_data ),
442+
.async_data_master_w_wptr_o ( async_cluster_to_soc_axi_bus.w_wptr ),
443+
.async_data_master_w_rptr_i ( async_cluster_to_soc_axi_bus.w_rptr ),
444+
.async_data_master_r_wptr_i ( async_cluster_to_soc_axi_bus.r_wptr ),
445+
.async_data_master_r_rptr_o ( async_cluster_to_soc_axi_bus.r_rptr ),
446+
.async_data_master_r_data_i ( async_cluster_to_soc_axi_bus.r_data ),
447+
.async_data_master_b_wptr_i ( async_cluster_to_soc_axi_bus.b_wptr ),
448+
.async_data_master_b_rptr_o ( async_cluster_to_soc_axi_bus.b_rptr ),
449+
.async_data_master_b_data_i ( async_cluster_to_soc_axi_bus.b_data ),
450+
.async_wide_master_aw_wptr_o ( async_dma_axi_bus.aw_wptr ),
451+
.async_wide_master_aw_rptr_i ( async_dma_axi_bus.aw_rptr ),
452+
.async_wide_master_aw_data_o ( async_dma_axi_bus.aw_data ),
453+
.async_wide_master_ar_wptr_o ( async_dma_axi_bus.ar_wptr ),
454+
.async_wide_master_ar_rptr_i ( async_dma_axi_bus.ar_rptr ),
455+
.async_wide_master_ar_data_o ( async_dma_axi_bus.ar_data ),
456+
.async_wide_master_w_data_o ( async_dma_axi_bus.w_data ),
457+
.async_wide_master_w_wptr_o ( async_dma_axi_bus.w_wptr ),
458+
.async_wide_master_w_rptr_i ( async_dma_axi_bus.w_rptr ),
459+
.async_wide_master_r_wptr_i ( async_dma_axi_bus.r_wptr ),
460+
.async_wide_master_r_rptr_o ( async_dma_axi_bus.r_rptr ),
461+
.async_wide_master_r_data_i ( async_dma_axi_bus.r_data ),
462+
.async_wide_master_b_wptr_i ( async_dma_axi_bus.b_wptr ),
463+
.async_wide_master_b_rptr_o ( async_dma_axi_bus.b_rptr ),
464+
.async_wide_master_b_data_i ( async_dma_axi_bus.b_data ),
465+
.async_data_slave_aw_wptr_i ( async_soc_to_cluster_axi_bus.aw_wptr ),
466+
.async_data_slave_aw_rptr_o ( async_soc_to_cluster_axi_bus.aw_rptr ),
467+
.async_data_slave_aw_data_i ( async_soc_to_cluster_axi_bus.aw_data ),
468+
.async_data_slave_ar_wptr_i ( async_soc_to_cluster_axi_bus.ar_wptr ),
469+
.async_data_slave_ar_rptr_o ( async_soc_to_cluster_axi_bus.ar_rptr ),
470+
.async_data_slave_ar_data_i ( async_soc_to_cluster_axi_bus.ar_data ),
471+
.async_data_slave_w_data_i ( async_soc_to_cluster_axi_bus.w_data ),
472+
.async_data_slave_w_wptr_i ( async_soc_to_cluster_axi_bus.w_wptr ),
473+
.async_data_slave_w_rptr_o ( async_soc_to_cluster_axi_bus.w_rptr ),
474+
.async_data_slave_r_wptr_o ( async_soc_to_cluster_axi_bus.r_wptr ),
475+
.async_data_slave_r_rptr_i ( async_soc_to_cluster_axi_bus.r_rptr ),
476+
.async_data_slave_r_data_o ( async_soc_to_cluster_axi_bus.r_data ),
477+
.async_data_slave_b_wptr_o ( async_soc_to_cluster_axi_bus.b_wptr ),
478+
.async_data_slave_b_rptr_i ( async_soc_to_cluster_axi_bus.b_rptr ),
479+
.async_data_slave_b_data_o ( async_soc_to_cluster_axi_bus.b_data )
480+
);
481+
482+
/* Error */
483+
`else
484+
$error("No cluster selected");
485+
`endif
486+
297487
endmodule

‎hw/chimera_cluster_adapter.sv‎

Lines changed: 33 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,9 @@ module chimera_cluster_adapter #(
3030

3131
) (
3232
input logic soc_clk_i,
33+
`ifndef TARGET_PULP_CLUSTER
3334
input logic clu_clk_i,
35+
`endif
3436
input logic rst_ni,
3537
// From SOC
3638
input narrow_in_req_t narrow_in_req_i,
@@ -265,7 +267,11 @@ module chimera_cluster_adapter #(
265267
.mst_req_t (clu_narrow_in_req_t),
266268
.mst_resp_t(clu_narrow_in_resp_t)
267269
) i_narrow_slv_to_narrow_mst_iw_converter (
270+
`ifndef TARGET_PULP_CLUSTER
268271
.clk_i (clu_clk_i),
272+
`else
273+
.clk_i (soc_clk_i),
274+
`endif
269275
.rst_ni (rst_ni),
270276
.slv_req_i (axi_to_cluster_narrow_req),
271277
.slv_resp_o(axi_to_cluster_narrow_resp),
@@ -294,7 +300,11 @@ module chimera_cluster_adapter #(
294300
.mst_req_t (narrow_out_req_t),
295301
.mst_resp_t (narrow_out_resp_t)
296302
) narrow_mst_iw_converter (
303+
`ifndef TARGET_PULP_CLUSTER
297304
.clk_i (clu_clk_i),
305+
`else
306+
.clk_i (soc_clk_i),
307+
`endif
298308
.rst_ni (rst_ni),
299309
.slv_req_i (axi_from_cluster_narrow_iwc_req),
300310
.slv_resp_o(axi_from_cluster_narrow_iwc_resp),
@@ -322,7 +332,11 @@ module chimera_cluster_adapter #(
322332
.mst_req_t (wide_out_req_t),
323333
.mst_resp_t (wide_out_resp_t)
324334
) wide_mst_iw_converter (
335+
`ifndef TARGET_PULP_CLUSTER
325336
.clk_i (clu_clk_i),
337+
`else
338+
.clk_i (soc_clk_i),
339+
`endif
326340
.rst_ni (rst_ni),
327341
.slv_req_i (axi_from_cluster_wide_iwc_req),
328342
.slv_resp_o(axi_from_cluster_wide_iwc_resp),
@@ -332,6 +346,7 @@ module chimera_cluster_adapter #(
332346

333347
// AXI Narrow CDC from SoC to Cluster
334348

349+
`ifndef TARGET_PULP_CLUSTER
335350
axi_cdc #(
336351
.aw_chan_t (axi_narrow_soc_in_aw_chan_t),
337352
.w_chan_t (axi_narrow_soc_in_w_chan_t),
@@ -351,9 +366,14 @@ module chimera_cluster_adapter #(
351366
.dst_req_o (axi_to_cluster_narrow_req),
352367
.dst_resp_i(axi_to_cluster_narrow_resp)
353368
);
369+
`else
370+
assign axi_to_cluster_narrow_req = narrow_in_req_i;
371+
assign narrow_in_resp_o = axi_to_cluster_narrow_resp;
372+
`endif
354373

355374
// AXI Narrow CDC from Cluster to SoC
356375

376+
`ifndef TARGET_PULP_CLUSTER
357377
axi_cdc #(
358378
.aw_chan_t (axi_narrow_soc_out_aw_chan_t),
359379
.w_chan_t (axi_narrow_soc_out_w_chan_t),
@@ -373,9 +393,14 @@ module chimera_cluster_adapter #(
373393
.dst_req_o (narrow_out_req_o[0]),
374394
.dst_resp_i(narrow_out_resp_i[0])
375395
);
396+
`else
397+
assign narrow_out_req_o[0] = axi_from_cluster_narrow_req;
398+
assign axi_from_cluster_narrow_resp = narrow_out_resp_i[0];
399+
`endif
376400

377401
// AXI Wide CDC from Cluster to SoC
378402

403+
`ifndef TARGET_PULP_CLUSTER
379404
axi_cdc #(
380405
.aw_chan_t (axi_wide_clu_out_aw_chan_t),
381406
.w_chan_t (axi_wide_clu_out_w_chan_t),
@@ -395,21 +420,27 @@ module chimera_cluster_adapter #(
395420
.dst_req_o (axi_from_cluster_wide_premux_req),
396421
.dst_resp_i(axi_from_cluster_wide_premux_resp)
397422
);
423+
`else
424+
assign axi_from_cluster_wide_premux_req = axi_from_cluster_wide_req;
425+
assign axi_from_cluster_wide_resp = axi_from_cluster_wide_premux_resp;
426+
`endif
398427

399428
// Validate parameters
400429
`ifndef VERILATOR
401430
`ifndef XSIM
402431

403432
write_wide_bypass :
404433
assert property (
405-
@(posedge clu_clk_i) ((axi_from_cluster_wide_premux_req.aw_valid & wide_mem_bypass_mode_i) |->
434+
@(posedge `ifndef TARGET_PULP_CLUSTER clu_clk_i `else soc_clk_i `endif)
435+
((axi_from_cluster_wide_premux_req.aw_valid & wide_mem_bypass_mode_i) |->
406436
(axi_from_cluster_wide_to_narrow_req.aw_valid &
407437
~axi_from_cluster_wide_memisl_req.aw_valid)))
408438
else $fatal(1, "Bypass Mode ON, but write request routed toward the Wide interconnect");
409439

410440
read_wide_bypass :
411441
assert property (
412-
@(posedge clu_clk_i) ((axi_from_cluster_wide_premux_req.ar_valid & wide_mem_bypass_mode_i) |->
442+
@(posedge `ifndef TARGET_PULP_CLUSTER clu_clk_i `else soc_clk_i `endif)
443+
((axi_from_cluster_wide_premux_req.ar_valid & wide_mem_bypass_mode_i) |->
413444
(axi_from_cluster_wide_to_narrow_req.ar_valid &
414445
~axi_from_cluster_wide_memisl_req.ar_valid)))
415446
else $fatal(1, "Bypass Mode ON, but read request routed toward the Wide interocnnect");

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