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sw: Adapt software to new systemRDL c-header chimera_addrmap.h 
1 parent 56e7ba4 commit ac9f120

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-258
lines changed

‎Makefile‎

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@@ -63,4 +63,5 @@ help:
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@echo -e ""
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@echo -e "Software:"
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@echo -e "${Green}chim-sw ${Black}Compile all software tests"
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@echo -e "${Green}chimera-addrmap ${Black}Regenerate c-header for SoC address map"
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@echo -e ""

‎chimera.mk‎

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@@ -56,6 +56,14 @@ $(CHIM_ROOT)/hw/bootrom/snitch/snitch_bootrom.bin: $(CHIM_ROOT)/hw/bootrom/snitc
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$(CHIM_ROOT)/hw/bootrom/snitch/snitch_bootrom.sv: $(CHIM_ROOT)/hw/bootrom/snitch/snitch_bootrom.bin $(CHS_ROOT)/util/gen_bootrom.py
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$(CHS_ROOT)/util/gen_bootrom.py --sv-module snitch_bootrom $< > $@
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#############
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# SystemRDL #
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#############
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CHIM_RDL_ALL += $(CHIM_ROOT)/hw/rdl/chimera.rdl
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CHIM_RDL_ALL += $(CHIM_ROOT)/hw/rdl/snitch_cluster.rdl
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CHIM_RDL_ALL += $(CHIM_ROOT)/hw/rdl/cheshire_host.rdl
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CHIM_RDL_ALL += $(CHIM_ROOT)/hw/rdl/chimera_regs.rdl
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.PHONY: regenerate_soc_regs
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regenerate_soc_regs: $(CHIM_ROOT)/hw/rdl/chimera_reg_top.sv $(CHIM_ROOT)/hw/rdl/chimera_reg_pkg.sv
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$(CHIM_ROOT)/hw/rdl/chimera_reg_top.sv $(CHIM_ROOT)/hw/rdl/chimera_reg_pkg.sv: $(CHIM_ROOT)/hw/rdl/chimera_regs.rdl

‎hw/rdl/cheshire_host.rdl‎

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// Copyright 2025 ETH Zurich and University of Bologna.
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// Solderpad Hardware License, Version 0.51, see LICENSE for details.
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// SPDX-License-Identifier: SHL-0.51
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`ifndef __CHESHIRE_HOST_RDL__
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`define __CHESHIRE_HOST_RDL__
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`include "chimera_regs.rdl"
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addrmap cheshire_host #(
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longint unsigned NumClusters = 1 // Number of Clusters
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) {
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chimera_regs #(.NumClusters (NumClusters)) chimera_regs @0x1000;
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// TODO: Map the Hyperbus
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// TODO: Map external reg for chip levelk (FLL, etc...)
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};
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`endif // __CHESHIRE_HOST_RDL__

‎hw/rdl/chimera.rdl‎

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// Copyright 2025 ETH Zurich and University of Bologna.
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// Solderpad Hardware License, Version 0.51, see LICENSE for details.
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// SPDX-License-Identifier: SHL-0.51
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`include "cheshire_host.rdl"
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`include "snitch_cluster.rdl"
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addrmap chimera_addrmap #(
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longint unsigned NumClusters = 1 // Number of Clusters
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){
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cheshire_host #(.NumClusters (NumClusters)) host @0x30000000;
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snitch_cluster snitch_cluster[NumClusters] @0x40000000 += 0x200000;
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external mem { mementries = 0x40000; memwidth = 8; } l2_mem_island @0x48000000;
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};

‎hw/rdl/chimera_regs.rdl‎

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`define CHIMERA_RDL
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addrmap chimera_regs #(
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longint unsigned NumClusters = 1 // Number of cores
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longint unsigned NumClusters = 1 // Number of clusters
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) {
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name = "chimera_regs";
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desc = "Chimera SoC control registers";

‎hw/rdl/snitch_cluster.rdl‎

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// Copyright 2025 ETH Zurich and University of Bologna.
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// Solderpad Hardware License, Version 0.51, see LICENSE for details.
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// SPDX-License-Identifier: SHL-0.51
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`ifndef __SNITCH_CLUSTER_RDL__
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`define __SNITCH_CLUSTER_RDL__
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// `include "snitch_cluster_wrapper.rdl"
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addrmap snitch_cluster {
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external mem {
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mementries = 1;
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memwidth = 64;
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} dummy;
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// snitch_cluster_wrapper #(.BASE_ADDR(0)) snitch_cluster_wrapper;
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};
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`endif // __SNITCH_CLUSTER_RDL__

‎sw/include/chimera_addrmap.h‎

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// Copyright 2025 ETH Zurich and University of Bologna.
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// Licensed under the Apache License, Version 2 0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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// Generated by PeakRDL-cheader - A free and open-source header generator
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// https://github.com/SystemRDL/PeakRDL-cheader
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#ifndef CHIMERA_ADDRMAP_H
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#define CHIMERA_ADDRMAP_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include <assert.h>
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// Reg - chimera_regs_NumClusters_5::snitch_boot_addr
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#define CHIMERA_REGS_NUMCLUSTERS_5__SNITCH_BOOT_ADDR__SNITCH_BOOT_ADDR_bm 0xffffffff
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#define CHIMERA_REGS_NUMCLUSTERS_5__SNITCH_BOOT_ADDR__SNITCH_BOOT_ADDR_bp 0
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#define CHIMERA_REGS_NUMCLUSTERS_5__SNITCH_BOOT_ADDR__SNITCH_BOOT_ADDR_bw 32
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#define CHIMERA_REGS_NUMCLUSTERS_5__SNITCH_BOOT_ADDR__SNITCH_BOOT_ADDR_reset 0xbadcab1e
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typedef union {
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struct __attribute__((__packed__)) {
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uint32_t SNITCH_BOOT_ADDR : 32;
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} f;
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uint32_t w;
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} chimera_regs_NumClusters_5__snitch_boot_addr_t;
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// Reg - chimera_regs_NumClusters_5::snitch_configurable_boot_addr
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#define CHIMERA_REGS_NUMCLUSTERS_5__SNITCH_CONFIGURABLE_BOOT_ADDR__SNITCH_CONFIGURABLE_BOOT_ADDR_bm \
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0xffffffff
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#define CHIMERA_REGS_NUMCLUSTERS_5__SNITCH_CONFIGURABLE_BOOT_ADDR__SNITCH_CONFIGURABLE_BOOT_ADDR_bp \
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0
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#define CHIMERA_REGS_NUMCLUSTERS_5__SNITCH_CONFIGURABLE_BOOT_ADDR__SNITCH_CONFIGURABLE_BOOT_ADDR_bw \
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32
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#define CHIMERA_REGS_NUMCLUSTERS_5__SNITCH_CONFIGURABLE_BOOT_ADDR__SNITCH_CONFIGURABLE_BOOT_ADDR_reset \
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0x30000000
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typedef union {
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struct __attribute__((__packed__)) {
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uint32_t SNITCH_CONFIGURABLE_BOOT_ADDR : 32;
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} f;
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uint32_t w;
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} chimera_regs_NumClusters_5__snitch_configurable_boot_addr_t;
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// Reg - chimera_regs_NumClusters_5::snitch_intr_handler_addr
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#define CHIMERA_REGS_NUMCLUSTERS_5__SNITCH_INTR_HANDLER_ADDR__SNITCH_INTR_HANDLER_ADDR_bm 0xffffffff
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#define CHIMERA_REGS_NUMCLUSTERS_5__SNITCH_INTR_HANDLER_ADDR__SNITCH_INTR_HANDLER_ADDR_bp 0
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#define CHIMERA_REGS_NUMCLUSTERS_5__SNITCH_INTR_HANDLER_ADDR__SNITCH_INTR_HANDLER_ADDR_bw 32
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#define CHIMERA_REGS_NUMCLUSTERS_5__SNITCH_INTR_HANDLER_ADDR__SNITCH_INTR_HANDLER_ADDR_reset \
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0xbadcab1e
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typedef union {
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struct __attribute__((__packed__)) {
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uint32_t SNITCH_INTR_HANDLER_ADDR : 32;
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} f;
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uint32_t w;
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} chimera_regs_NumClusters_5__snitch_intr_handler_addr_t;
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// Reg - chimera_regs_NumClusters_5::snitch_cluster_return
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#define CHIMERA_REGS_NUMCLUSTERS_5__SNITCH_CLUSTER_RETURN__SNITCH_CLUSTER_RETURN_bm 0xffffffff
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#define CHIMERA_REGS_NUMCLUSTERS_5__SNITCH_CLUSTER_RETURN__SNITCH_CLUSTER_RETURN_bp 0
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#define CHIMERA_REGS_NUMCLUSTERS_5__SNITCH_CLUSTER_RETURN__SNITCH_CLUSTER_RETURN_bw 32
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#define CHIMERA_REGS_NUMCLUSTERS_5__SNITCH_CLUSTER_RETURN__SNITCH_CLUSTER_RETURN_reset 0x0
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typedef union {
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struct __attribute__((__packed__)) {
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uint32_t SNITCH_CLUSTER_RETURN : 32;
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} f;
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uint32_t w;
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} chimera_regs_NumClusters_5__snitch_cluster_return_t;
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// Reg - chimera_regs_NumClusters_5::reset_cluster
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#define CHIMERA_REGS_NUMCLUSTERS_5__RESET_CLUSTER__RESET_CLUSTER_bm 0x1
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#define CHIMERA_REGS_NUMCLUSTERS_5__RESET_CLUSTER__RESET_CLUSTER_bp 0
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#define CHIMERA_REGS_NUMCLUSTERS_5__RESET_CLUSTER__RESET_CLUSTER_bw 1
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#define CHIMERA_REGS_NUMCLUSTERS_5__RESET_CLUSTER__RESET_CLUSTER_reset 0x1
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typedef union {
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struct __attribute__((__packed__)) {
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uint32_t RESET_CLUSTER : 1;
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uint32_t : 31;
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} f;
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uint32_t w;
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} chimera_regs_NumClusters_5__reset_cluster_t;
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// Reg - chimera_regs_NumClusters_5::cluster_clk_gate_en
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#define CHIMERA_REGS_NUMCLUSTERS_5__CLUSTER_CLK_GATE_EN__CLUSTER_CLK_GATE_EN_bm 0x1
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#define CHIMERA_REGS_NUMCLUSTERS_5__CLUSTER_CLK_GATE_EN__CLUSTER_CLK_GATE_EN_bp 0
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#define CHIMERA_REGS_NUMCLUSTERS_5__CLUSTER_CLK_GATE_EN__CLUSTER_CLK_GATE_EN_bw 1
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#define CHIMERA_REGS_NUMCLUSTERS_5__CLUSTER_CLK_GATE_EN__CLUSTER_CLK_GATE_EN_reset 0x1
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typedef union {
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struct __attribute__((__packed__)) {
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uint32_t CLUSTER_CLK_GATE_EN : 1;
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uint32_t : 31;
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} f;
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uint32_t w;
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} chimera_regs_NumClusters_5__cluster_clk_gate_en_t;
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// Reg - chimera_regs_NumClusters_5::wide_mem_cluster_bypass
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#define CHIMERA_REGS_NUMCLUSTERS_5__WIDE_MEM_CLUSTER_BYPASS__WIDE_MEM_CLUSTER_BYPASS_bm 0x1
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#define CHIMERA_REGS_NUMCLUSTERS_5__WIDE_MEM_CLUSTER_BYPASS__WIDE_MEM_CLUSTER_BYPASS_bp 0
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#define CHIMERA_REGS_NUMCLUSTERS_5__WIDE_MEM_CLUSTER_BYPASS__WIDE_MEM_CLUSTER_BYPASS_bw 1
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#define CHIMERA_REGS_NUMCLUSTERS_5__WIDE_MEM_CLUSTER_BYPASS__WIDE_MEM_CLUSTER_BYPASS_reset 0x0
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typedef union {
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struct __attribute__((__packed__)) {
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uint32_t WIDE_MEM_CLUSTER_BYPASS : 1;
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uint32_t : 31;
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} f;
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uint32_t w;
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} chimera_regs_NumClusters_5__wide_mem_cluster_bypass_t;
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// Reg - chimera_regs_NumClusters_5::cluster_busy
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#define CHIMERA_REGS_NUMCLUSTERS_5__CLUSTER_BUSY__CLUSTER_BUSY_bm 0x1
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#define CHIMERA_REGS_NUMCLUSTERS_5__CLUSTER_BUSY__CLUSTER_BUSY_bp 0
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#define CHIMERA_REGS_NUMCLUSTERS_5__CLUSTER_BUSY__CLUSTER_BUSY_bw 1
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#define CHIMERA_REGS_NUMCLUSTERS_5__CLUSTER_BUSY__CLUSTER_BUSY_reset 0x0
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typedef union {
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struct __attribute__((__packed__)) {
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uint32_t CLUSTER_BUSY : 1;
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uint32_t : 31;
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} f;
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uint32_t w;
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} chimera_regs_NumClusters_5__cluster_busy_t;
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// Addrmap - chimera_regs_NumClusters_5
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typedef struct __attribute__((__packed__)) {
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chimera_regs_NumClusters_5__snitch_boot_addr_t snitch_boot_addr;
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chimera_regs_NumClusters_5__snitch_configurable_boot_addr_t snitch_configurable_boot_addr;
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chimera_regs_NumClusters_5__snitch_intr_handler_addr_t snitch_intr_handler_addr;
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chimera_regs_NumClusters_5__snitch_cluster_return_t snitch_cluster_return[5];
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chimera_regs_NumClusters_5__reset_cluster_t reset_cluster[5];
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chimera_regs_NumClusters_5__cluster_clk_gate_en_t cluster_clk_gate_en[5];
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chimera_regs_NumClusters_5__wide_mem_cluster_bypass_t wide_mem_cluster_bypass[5];
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chimera_regs_NumClusters_5__cluster_busy_t cluster_busy[5];
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} chimera_regs_NumClusters_5_t;
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// Addrmap - cheshire_host_NumClusters_5
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typedef struct __attribute__((__packed__)) {
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uint8_t RESERVED_0_fff[0x1000];
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chimera_regs_NumClusters_5_t chimera_regs;
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} cheshire_host_NumClusters_5_t;
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// Mem - snitch_cluster::dummy
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typedef struct __attribute__((__packed__)) {
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uint64_t mem[1];
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} snitch_cluster__dummy_t;
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// Addrmap - snitch_cluster
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typedef struct __attribute__((__packed__)) {
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snitch_cluster__dummy_t dummy;
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uint8_t RESERVED_8_1fffff[0x1ffff8];
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} snitch_cluster__stride200000_t;
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// Mem - chimera_addrmap_NumClusters_5::l2_mem_island
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typedef struct __attribute__((__packed__)) {
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uint8_t mem[262144];
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} chimera_addrmap_NumClusters_5__l2_mem_island_t;
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// Addrmap - chimera_addrmap_NumClusters_5
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typedef struct __attribute__((__packed__)) {
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uint8_t RESERVED_0_2fffffff[0x30000000];
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cheshire_host_NumClusters_5_t host;
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uint8_t RESERVED_30001070_3fffffff[0xfffef90];
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snitch_cluster__stride200000_t snitch_cluster[5];
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uint8_t RESERVED_40a00000_47ffffff[0x7600000];
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chimera_addrmap_NumClusters_5__l2_mem_island_t l2_mem_island;
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} chimera_addrmap_NumClusters_5_t;
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// Instances
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#define chimera_addrmap (*(volatile chimera_addrmap_NumClusters_5_t *)0x0UL)
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static_assert(sizeof(chimera_addrmap_NumClusters_5_t) == 0x48040000, "Packing error");
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#ifdef __cplusplus
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}
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#endif
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#endif /* CHIMERA_ADDRMAP_H */

‎sw/include/offload.h‎

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#include <stdint.h>
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void setupInterruptHandler(void *handler);
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void setClusterClockGating(uint8_t *regPtr, uint8_t clusterId, bool enable);
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void setAllClusterClockGating(uint8_t *regPtr, bool enable);
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void setClusterReset(uint8_t *regPtr, uint8_t clusterId, bool enable);
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void setAllClusterReset(uint8_t *regPtr, bool enable);
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void setClusterClockGating(uint8_t clusterId, bool enable);
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void setAllClusterClockGating(volatile uint8_t numRegs, bool enable);
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void setClusterReset(uint8_t clusterId, bool enable);
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void setAllClusterReset(volatile uint8_t numRegs, bool enable);
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void setAllRegs(volatile uint32_t *regPtr, uint8_t numRegs, bool enable);
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void offloadToCluster(void *function, uint8_t hartId);
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void waitClusterBusy(uint8_t clusterId);
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uint32_t waitForCluster(uint8_t clusterId);

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