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sw: Test addressability and user-defined offload to PULP Cluster
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‎sw/tests/testClusterAddr_pulp.c‎

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// Copyright 2024 ETH Zurich and University of Bologna.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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//
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// Sergio Mazzola <[email protected]>
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// Simple addressability test which writes and subsequently reads a value
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// in the first address mapped to the PULP Cluster 0 (i.e., the first
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// TCDM address)
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#include "offload.h"
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#include "soc_addr_map.h"
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#include <regs/soc_ctrl.h>
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#include <stdint.h>
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#define TESTVAL_CLUSTER 0xdeadbeef
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int main() {
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uint8_t *base_addr_tcdm_cluster_0 = CLUSTER_0_BASE;
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*((uint32_t*)base_addr_tcdm_cluster_0) = TESTVAL_CLUSTER;
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asm volatile ("nop");
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asm volatile ("nop");
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asm volatile ("nop");
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asm volatile ("nop");
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asm volatile ("nop");
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uint32_t result = *((uint32_t*)base_addr_tcdm_cluster_0);
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if (result == TESTVAL_CLUSTER) {
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return 0;
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} else {
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return 1;
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}
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}

‎sw/tests/testClusterOffload_pulp.c‎

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// Copyright 2024 ETH Zurich and University of Bologna.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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//
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// Sergio Mazzola <[email protected]>
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// Simple offload test to PULP Cluster 0. First set the boot address of all 8
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// cluster cores to the desired one (the simple test function), then enables the
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// fetch enable for all cores at the same time. All this is done through writes
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// to the cluster's peripheral interconnect. Does not currently take care of the
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// cluster return value.
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#include "offload.h"
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#include "soc_addr_map.h"
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#include <regs/soc_ctrl.h>
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#include <stdint.h>
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#define TESTVAL_CLUSTER 0xdeadbeef
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#define PERIPH_OFFSET 0x00200000
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#define FETCH_EN_OFFSET (PERIPH_OFFSET + 0x008)
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#define BOOT_ADDR_CORE_0_OFFSET (PERIPH_OFFSET + 0x040)
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#define BOOT_ADDR_CORE_1_OFFSET (PERIPH_OFFSET + 0x044)
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#define BOOT_ADDR_CORE_2_OFFSET (PERIPH_OFFSET + 0x048)
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#define BOOT_ADDR_CORE_3_OFFSET (PERIPH_OFFSET + 0x04C)
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#define BOOT_ADDR_CORE_4_OFFSET (PERIPH_OFFSET + 0x050)
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#define BOOT_ADDR_CORE_5_OFFSET (PERIPH_OFFSET + 0x054)
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#define BOOT_ADDR_CORE_6_OFFSET (PERIPH_OFFSET + 0x058)
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#define BOOT_ADDR_CORE_7_OFFSET (PERIPH_OFFSET + 0x05C)
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#define BOOT_ADDR_CORE_8_OFFSET (PERIPH_OFFSET + 0x060)
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#define BOOT_ADDR_CORE_9_OFFSET (PERIPH_OFFSET + 0x064)
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#define BOOT_ADDR_CORE_10_OFFSET (PERIPH_OFFSET + 0x068)
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#define BOOT_ADDR_CORE_11_OFFSET (PERIPH_OFFSET + 0x06C)
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#define BOOT_ADDR_CORE_12_OFFSET (PERIPH_OFFSET + 0x070)
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#define BOOT_ADDR_CORE_13_OFFSET (PERIPH_OFFSET + 0x074)
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#define BOOT_ADDR_CORE_14_OFFSET (PERIPH_OFFSET + 0x078)
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#define BOOT_ADDR_CORE_15_OFFSET (PERIPH_OFFSET + 0x07C)
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int32_t test_cluster() {
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int32_t result;
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int32_t hart_id;
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asm volatile ("csrr %0, mhartid" : "=r"(hart_id)::);
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asm volatile (
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"li t0, %1\n" // Load immediate value into t0
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"mv a0, t0\n" // Move t0 into a0 (x10)
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"mv %0, a0\n" // Move a0 into the output variable
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: "=r"(result) // Output operand
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: "i"(TESTVAL_CLUSTER) // Input operand: immediate value
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: "t0", "a0" // Clobbered registers
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);
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result = result + hart_id;
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return result;
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}
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int main() {
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int32_t hart_id;
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asm volatile ("csrr %0, mhartid" : "=r"(hart_id)::);
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// set boot address of all cores in cluster 0
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uint8_t *boot_addr_core_0_cluster_0 = CLUSTER_0_BASE + BOOT_ADDR_CORE_0_OFFSET;
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uint8_t *boot_addr_core_1_cluster_0 = CLUSTER_0_BASE + BOOT_ADDR_CORE_1_OFFSET;
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uint8_t *boot_addr_core_2_cluster_0 = CLUSTER_0_BASE + BOOT_ADDR_CORE_2_OFFSET;
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uint8_t *boot_addr_core_3_cluster_0 = CLUSTER_0_BASE + BOOT_ADDR_CORE_3_OFFSET;
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uint8_t *boot_addr_core_4_cluster_0 = CLUSTER_0_BASE + BOOT_ADDR_CORE_4_OFFSET;
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uint8_t *boot_addr_core_5_cluster_0 = CLUSTER_0_BASE + BOOT_ADDR_CORE_5_OFFSET;
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uint8_t *boot_addr_core_6_cluster_0 = CLUSTER_0_BASE + BOOT_ADDR_CORE_6_OFFSET;
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uint8_t *boot_addr_core_7_cluster_0 = CLUSTER_0_BASE + BOOT_ADDR_CORE_7_OFFSET;
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*((uint32_t*)boot_addr_core_0_cluster_0) = test_cluster;
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*((uint32_t*)boot_addr_core_1_cluster_0) = test_cluster;
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*((uint32_t*)boot_addr_core_2_cluster_0) = test_cluster;
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*((uint32_t*)boot_addr_core_3_cluster_0) = test_cluster;
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*((uint32_t*)boot_addr_core_4_cluster_0) = test_cluster;
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*((uint32_t*)boot_addr_core_5_cluster_0) = test_cluster;
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*((uint32_t*)boot_addr_core_6_cluster_0) = test_cluster;
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*((uint32_t*)boot_addr_core_7_cluster_0) = test_cluster;
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// enable fetch for all cores in cluster 0
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uint8_t *fetch_en_cluster_0 = CLUSTER_0_BASE + FETCH_EN_OFFSET;
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*((uint32_t*)fetch_en_cluster_0) = 0x00FF;
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// only the host hart executes this
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volatile int count = 10000;
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if (hart_id == 0) {
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// delay loop
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asm volatile (
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"1: nop\n"
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"addi %0, %0, -1\n"
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"bnez %0, 1b\n"
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: "+r"(count) // Input and output operand
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);
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}
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return count;
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}

‎target/sim/vsim/setup.chimera_soc.tcl‎

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#
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# Moritz Scherer <[email protected]>
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set BINARY ../../../sw/tests/testCluster.memisl.elf
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set BINARY ../../../sw/tests/testClusterAddr_pulp.memisl.elf
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set SELCFG 0

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