Release v3.1

This release includes the following new features:

• Add a default construction of the UltraScale hardware: this is needed for those Kria instances that are not configured for dynamic reconfiguration. In this case, the UltraScale can start without a bitstream. It adds an IHardware::Create(HardwareArchitecture hw) that does not receive the bitstream.
• Add a zero address DMA: this is also for this case, where we need to allocate memory, but DMA does not move it.

Pending:

• Other platforms: xdma-based FPGAs not supported by XRT
• Multi-device support
• xsa file support
• AXI GPIO instances

Release v0.3

This release includes the following new features:

• [new!] Support for Work Queues: this support allows to have different execution streams, quite similar to CUDA Streams. By default, they execute in the default program workflow. Some examples: ad08-streams, ad08-sequential.
• [new!] Introduction to Clock Adjustment (ZYNQ only): this support allows the increase of clock speed of the PL according to a desired clock speed. This allows for saving energy when high performance is not mandatory. Moreover, it can adjust the clock to the maximum performance of the design. An example: matrix-multiplication

Pending:

• Other platforms: xdma-based FPGAs not supported by XRT
• Multi-device support
• xsa file support

Release v0.2

This is the second release of CYNQ. It includes:

• [new!] Support for Xilinx Alveo cards
• Improved AXI-MM support in Xilinx Kria / US+
• [new!] Support for xclbin memory

Pending:

• Other platforms: xdma-based FPGAs not supported by XRT
• Work queue
• Multi-device support

Release v0.1

This is the first release of CYNQ. It includes:

• Xilinx Kria Support
• Support for bitstream overlay

Pending:

• Support for XCLBin
• Support for AXI Full memory
• Other platforms
• Queues