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incremental_db
incremental_db
 
 
AES.qpf
AES.qpf
 
 
AES.qsf
AES.qsf
 
 
AES.qws
AES.qws
 
 
AES.v
AES.v
 
 
AES.v.bak
AES.v.bak
 
 
AES_assignment_defaults.qdf
AES_assignment_defaults.qdf
 
 
AES_description.txt
AES_description.txt
 
 
AES_nativelink_simulation.rpt
AES_nativelink_simulation.rpt
 
 
AddRoundKey.v
AddRoundKey.v
 
 
AddRoundKey.v.bak
AddRoundKey.v.bak
 
 
BlockTostate.v
BlockTostate.v
 
 
InvMixColumns.v
InvMixColumns.v
 
 
InvMixColumns.v.bak
InvMixColumns.v.bak
 
 
Inv_cipher.v
Inv_cipher.v
 
 
Inv_cipher.v.bak
Inv_cipher.v.bak
 
 
InverseShiftRows.v
InverseShiftRows.v
 
 
InverseShiftRows.v.bak
InverseShiftRows.v.bak
 
 
KeyExpansion.v
KeyExpansion.v
 
 
KeyExpansion.v.bak
KeyExpansion.v.bak
 
 
MixColumns.v
MixColumns.v
 
 
MixColumns.v.bak
MixColumns.v.bak
 
 
README.md
README.md
 
 
RotWord.v
RotWord.v
 
 
RotWord.v.bak
RotWord.v.bak
 
 
ShiftRows.v
ShiftRows.v
 
 
ShiftRows.v.bak
ShiftRows.v.bak
 
 
Test_bench.v
Test_bench.v
 
 
Test_bench.v.bak
Test_bench.v.bak
 
 
Wrapper.v
Wrapper.v
 
 
Wrapper.v.bak
Wrapper.v.bak
 
 
c5_pin_model_dump.txt
c5_pin_model_dump.txt
 
 
cipher.v
cipher.v
 
 
cipher.v.bak
cipher.v.bak
 
 
subBytes.v
subBytes.v
 
 
subBytes.v.bak
subBytes.v.bak
 
 
subBytes_inv.v
subBytes_inv.v
 
 
subBytes_inv.v.bak
subBytes_inv.v.bak
 
 

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Advanced-Encryption-Standard-in-Verilog

Implemented an Advanced Encryption System (AES) using Verilog, demonstrating proficiency in hardware descriptionlanguage. Developed a robust and efficient encryption system, showcasing skills in digital design and hardwareprogramming.

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