Array Builder Tool - Replicate Optimized Kernels in an Array #1163
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Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
…ray_builder Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Eddie Hung <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
…ray_builder Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
#1291) * Add ability for PerformanceExplorer to ensure external routability with InlineFlopTools Signed-off-by: Andrew Butt <[email protected]> * Add ability to place flip-flops around array in array_builder to make out_of_context designs more realistic Signed-off-by: Andrew Butt <[email protected]> * Add automatic PBlock selection and allow 5 inline flip-flops to be placed in a slice Signed-off-by: Andrew Butt <[email protected]> * Add option to specify whether ArrayBuilder design in OOC Signed-off-by: Andrew Butt <[email protected]> * Refactor getNetsWithOverlappingNodes Signed-off-by: Andrew Butt <[email protected]> * Fix java 8 compat Signed-off-by: Andrew Butt <[email protected]> * Address comments Signed-off-by: Andrew Butt <[email protected]> * Swap order of SLICE and DSP checks Co-authored-by: Chris Lavin <[email protected]> Signed-off-by: Andrew Butt <[email protected]> * Prevent flops from being added to the clock on fully ooc designs (no ibuf on clock) Signed-off-by: Andrew Butt <[email protected]> --------- Signed-off-by: Andrew Butt <[email protected]> Signed-off-by: Andrew Butt <[email protected]> Co-authored-by: Andrew Butt <[email protected]> Co-authored-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Andrew Butt <[email protected]>
…to 2.20.0 (#1306) * Testing updated 3rd party packages Signed-off-by: Chris Lavin <[email protected]> * Minor additions to DesignComparator Signed-off-by: Chris Lavin <[email protected]> * Update license to reflect new/updated packages Signed-off-by: Chris Lavin <[email protected]> * rc1 jar Signed-off-by: Chris Lavin <[email protected]> * Fix failing DesignComparator test. Signed-off-by: Chris Lavin <[email protected]> * Address review comments Signed-off-by: Chris Lavin <[email protected]> --------- Signed-off-by: Chris Lavin <[email protected]>
* [ECOTools] disconnectNet() to use skipUnrouteIntraSite property Full property: rapidwright.ecotools.disconnectNet.skipUnrouteIntraSite Signed-off-by: Eddie Hung <[email protected]> * Fix comment Signed-off-by: Eddie Hung <[email protected]> * [TestCell] Add testGetAllCorrespondingSitePinNamesLUTRouteThru() Signed-off-by: Eddie Hung <[email protected]> --------- Signed-off-by: Eddie Hung <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
* Full TCL parser for XDC Signed-off-by: Jakob Wenzel <[email protected]> * Testing updated 3rd party packages Signed-off-by: Chris Lavin <[email protected]> * Minor additions to DesignComparator Signed-off-by: Chris Lavin <[email protected]> * Update license to reflect new/updated packages Signed-off-by: Chris Lavin <[email protected]> * rc1 jar Signed-off-by: Chris Lavin <[email protected]> * Fix failing DesignComparator test. Signed-off-by: Chris Lavin <[email protected]> * Adds Jacl 1.4.1 as a library dependency Signed-off-by: Chris Lavin <[email protected]> * Address review comments Signed-off-by: Chris Lavin <[email protected]> * add more jacadoc, refactor to own package Signed-off-by: Jakob Wenzel <[email protected]> * 2025.2.0-rc2 jar with refactored XDCParser reference in Design.writeCheckpoint() Signed-off-by: Chris Lavin <[email protected]> * Add vertical clock spine printing and clock root detection (#1314) * Add vertical clock spine printing and clock root detection Signed-off-by: Andrew Butt <[email protected]> * Update comments Signed-off-by: Andrew Butt <[email protected]> * Add test for findClockRootVRoute Signed-off-by: Andrew Butt <[email protected]> * Update test/src/com/xilinx/rapidwright/design/TestNetTools.java Co-authored-by: Chris Lavin <[email protected]> Signed-off-by: Andrew Butt <[email protected]> * Update test/src/com/xilinx/rapidwright/design/TestNetTools.java Co-authored-by: Chris Lavin <[email protected]> Signed-off-by: Andrew Butt <[email protected]> --------- Signed-off-by: Andrew Butt <[email protected]> Signed-off-by: Andrew Butt <[email protected]> Co-authored-by: Chris Lavin <[email protected]> * Apply suggestions from code review Co-authored-by: Chris Lavin <[email protected]> Signed-off-by: Jakob Wenzel <[email protected]> * [PBlock] Add IsSoft and ExcludePlacement property in pblock (#1315) * [PBlock] Add IsSoft and ExcludePlacement property in pblock Signed-off-by: coherent17 <[email protected]> * [PBlock] Update getTclConstraints Signed-off-by: coherent17 <[email protected]> * [PBlock] reuse dcp in RapidWrightDCP to run test Signed-off-by: coherent17 <[email protected]> * [PblockProperty] Relocate PblockProperty and add unit test to test TclConstraints Signed-off-by: coherent17 <[email protected]> * [PblockProperty] Remove toString in PblockProperty Signed-off-by: coherent17 <[email protected]> --------- Signed-off-by: coherent17 <[email protected]> * apply more review suggestions Signed-off-by: Jakob Wenzel <[email protected]> * link to class documentation for lookup Signed-off-by: Jakob Wenzel <[email protected]> * add testcase Signed-off-by: Jakob Wenzel <[email protected]> * Test constraints for parsing, stringifying and then parsing again Signed-off-by: Jakob Wenzel <[email protected]> * add missing license header Signed-off-by: Jakob Wenzel <[email protected]> * parse pblocks with XDCParser Signed-off-by: Jakob Wenzel <[email protected]> * fix wrong import, fix license headers Signed-off-by: Jakob Wenzel <[email protected]> * check XDCParser against all DCPs in RapidWrightDCP Signed-off-by: Jakob Wenzel <[email protected]> * 2025.2.0-rc3, fixes #1320 Signed-off-by: Chris Lavin <[email protected]> * add roundtrip testing to TestConstraintTools Signed-off-by: Jakob Wenzel <[email protected]> * test roundtrip for all xdc, speed up get_cells Signed-off-by: Jakob Wenzel <[email protected]> * Updating reference to RapidWrightDCP Signed-off-by: Chris Lavin <[email protected]> --------- Signed-off-by: Jakob Wenzel <[email protected]> Signed-off-by: Chris Lavin <[email protected]> Signed-off-by: Andrew Butt <[email protected]> Signed-off-by: Andrew Butt <[email protected]> Signed-off-by: coherent17 <[email protected]> Co-authored-by: Chris Lavin <[email protected]> Co-authored-by: Andrew Butt <[email protected]> Co-authored-by: Chris Lavin <[email protected]> Co-authored-by: Coherent17 <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
* Only remove top level Vivado bus prevention annotations Signed-off-by: Andrew Butt <[email protected]> * Update src/com/xilinx/rapidwright/edif/EDIFCell.java Co-authored-by: Chris Lavin <[email protected]> Signed-off-by: Andrew Butt <[email protected]> * Update javadoc Signed-off-by: Andrew Butt <[email protected]> --------- Signed-off-by: Andrew Butt <[email protected]> Signed-off-by: Andrew Butt <[email protected]> Co-authored-by: Chris Lavin <[email protected]>
* [EDIFPort] Refactor getBitBlastedIndices() Signed-off-by: Chris Lavin <[email protected]> * Check if isBus() Signed-off-by: Chris Lavin <[email protected]> * Update src/com/xilinx/rapidwright/edif/EDIFPort.java Co-authored-by: eddieh-xlnx <[email protected]> Signed-off-by: Chris Lavin <[email protected]> * Fixing chronic misspelling of indices Signed-off-by: Chris Lavin <[email protected]> * Update src/com/xilinx/rapidwright/edif/EDIFPort.java Co-authored-by: eddieh-xlnx <[email protected]> Signed-off-by: Chris Lavin <[email protected]> --------- Signed-off-by: Chris Lavin <[email protected]> Co-authored-by: eddieh-xlnx <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
* Initial Schematic viewer with several issues. Signed-off-by: Chris Lavin <[email protected]> * Fix minor issues Signed-off-by: Chris Lavin <[email protected]> * Fixes minor rendering issues Signed-off-by: Chris Lavin <[email protected]> * Fixes around labeling and refactoring Signed-off-by: Chris Lavin <[email protected]> * Fix top port labels Signed-off-by: Chris Lavin <[email protected]> * Fix hier-cell pin labels Signed-off-by: Chris Lavin <[email protected]> * Fix hier button, still needs work for internal routes Signed-off-by: Chris Lavin <[email protected]> * Fixes nets inside expanded cells Signed-off-by: Chris Lavin <[email protected]> * Move button to top left corner of expanded cells Signed-off-by: Chris Lavin <[email protected]> * Fix padding/spacing around labels and buttons Signed-off-by: Chris Lavin <[email protected]> * Fixing multiple hier view, switch from EDIFCell->EDIFHierCellInst Signed-off-by: Chris Lavin <[email protected]> * Basic selection using Strings, still WIP Signed-off-by: Chris Lavin <[email protected]> * Fixes various bugs Signed-off-by: Chris Lavin <[email protected]> * Refactor to use all EDIFHier classes Signed-off-by: Chris Lavin <[email protected]> * Fix disconnected ports Signed-off-by: Chris Lavin <[email protected]> * Fix NPE Signed-off-by: Chris Lavin <[email protected]> * Fix multi-level hierarchy issue. Signed-off-by: Chris Lavin <[email protected]> * Fixing Z layers Signed-off-by: Chris Lavin <[email protected]> * Update for ELK and Guava license inclusion. Signed-off-by: Chris Lavin <[email protected]> * Cleanup Signed-off-by: Chris Lavin <[email protected]> * Temporarily remove cache Signed-off-by: Chris Lavin <[email protected]> * Restore cache entry Signed-off-by: Chris Lavin <[email protected]> * Update Jar test Signed-off-by: Chris Lavin <[email protected]> * List jars Signed-off-by: Chris Lavin <[email protected]> * Rename cache Signed-off-by: Chris Lavin <[email protected]> * Try new gradle home dir Signed-off-by: Chris Lavin <[email protected]> * More debug Signed-off-by: Chris Lavin <[email protected]> * Remove env Signed-off-by: Chris Lavin <[email protected]> * Fix NPE on inner port Signed-off-by: Chris Lavin <[email protected]> * Enable top selection Signed-off-by: Chris Lavin <[email protected]> * Add zoom to fit when selecting a new cell. Signed-off-by: Chris Lavin <[email protected]> * Workaround to support JDK8 execution with ELK Signed-off-by: Chris Lavin <[email protected]> * Fix selection of unexpanded tree items Signed-off-by: Chris Lavin <[email protected]> * Simplify Signed-off-by: Chris Lavin <[email protected]> * Attempt to allow selection from Python prompt Signed-off-by: Chris Lavin <[email protected]> * Select from main thread Signed-off-by: Chris Lavin <[email protected]> * get startup sync correct Signed-off-by: Chris Lavin <[email protected]> * Fixing more issues, still WIP Signed-off-by: Chris Lavin <[email protected]> * Fix missing top-level ports in the tree browser. Signed-off-by: Chris Lavin <[email protected]> * Fix various NPEs, top port issues Signed-off-by: Chris Lavin <[email protected]> * Cleanup after window closes Signed-off-by: Chris Lavin <[email protected]> * Adds right-click copy menu on tree items Signed-off-by: Chris Lavin <[email protected]> --------- Signed-off-by: Chris Lavin <[email protected]>
* Updates for 2025.2.0 devices Signed-off-by: Chris Lavin <[email protected]> * Update 2025.2.0 devices Signed-off-by: Chris Lavin <[email protected]> * rc4 Signed-off-by: Chris Lavin <[email protected]> * rc5 Signed-off-by: Chris Lavin <[email protected]> --------- Signed-off-by: Chris Lavin <[email protected]>
#1294) * Adds external library for netlists to compensate for black boxed cells Signed-off-by: Chris Lavin <[email protected]> * Removing overconstrained check Signed-off-by: Chris Lavin <[email protected]> * Add additional validity check in new EDIFPortInst() Signed-off-by: Chris Lavin <[email protected]> * Fix failing test case after EDIFPortInst check Signed-off-by: Chris Lavin <[email protected]> * Adds support for negative indexed busses on ports Signed-off-by: Chris Lavin <[email protected]> * Adds example test of how to run Signed-off-by: Chris Lavin <[email protected]> * Skip multiply_ip.dcp Signed-off-by: Chris Lavin <[email protected]> * Test fix Signed-off-by: Chris Lavin <[email protected]> * Updating RapidWrightDCP Signed-off-by: Chris Lavin <[email protected]> --------- Signed-off-by: Chris Lavin <[email protected]>
…#1326) Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
* Parallelize router initialization Signed-off-by: Andrew Butt <[email protected]> * Start improving parallelism Signed-off-by: Andrew Butt <[email protected]> * Parallelize createMissingSitePinInsts Signed-off-by: Andrew Butt <[email protected]> * Clean up parallelization Signed-off-by: Andrew Butt <[email protected]> * Switch to using futures to prevent accidentally hiding exceptions thrown in threads Signed-off-by: Andrew Butt <[email protected]> * Fix NPE Signed-off-by: Andrew Butt <[email protected]> * Fix concurrent modification issues Signed-off-by: Andrew Butt <[email protected]> * Fix another concurrent modification issue Signed-off-by: Andrew Butt <[email protected]> * Reduce synchronization and add caching on cells and pins Signed-off-by: Andrew Butt <[email protected]> * Address comments Signed-off-by: Andrew Butt <[email protected]> * Add back sync Signed-off-by: Andrew Butt <[email protected]> * Trying to fix failing test case Signed-off-by: Andrew Butt <[email protected]> * Fix accidentally skipping some nets Signed-off-by: Andrew Butt <[email protected]> * Cleanup Signed-off-by: Andrew Butt <[email protected]> * Add synchronization for rare case Signed-off-by: Andrew Butt <[email protected]> * Remove fall-through if statements Signed-off-by: Andrew Butt <[email protected]> * Fix additional early returns Signed-off-by: Andrew Butt <[email protected]> * Use join instead of joinFirst Signed-off-by: Andrew Butt <[email protected]> * remove cell cache Signed-off-by: Andrew Butt <[email protected]> * Remove re-lookup of cell Signed-off-by: Andrew Butt <[email protected]> * Switch to integer map Signed-off-by: Andrew Butt <[email protected]> * Fix bug from switching to integer site wires map Signed-off-by: Andrew Butt <[email protected]> * Cleanup Signed-off-by: Andrew Butt <[email protected]> * Add back site wires copy Signed-off-by: Andrew Butt <[email protected]> * Add comment on synchronization Signed-off-by: Andrew Butt <[email protected]> * [DesignTools] Simplify Simplify createMissingSitePinInsts() Change getAllRoutedSitePinsFromPhysicalPin() Remove getSiteInstToNetSiteWiresMap() Signed-off-by: Eddie Hung <[email protected]> * Cleanup Signed-off-by: Eddie Hung <[email protected]> * Comments Signed-off-by: Eddie Hung <[email protected]> * createMissingSitePinInsts() to depend on makePhysNetNameConsistent() Thereby not needing to do parent net checks Signed-off-by: Eddie Hung <[email protected]> * Cleanup Signed-off-by: Eddie Hung <[email protected]> * Fix tests Signed-off-by: Eddie Hung <[email protected]> * Undo accidental Signed-off-by: Eddie Hung <[email protected]> * [MergeDesigns] Clear logical net from physical net Signed-off-by: Eddie Hung <[email protected]> * Double check before renaming Signed-off-by: Eddie Hung <[email protected]> * Tidy Signed-off-by: Eddie Hung <[email protected]> * getSitePinInst() to be synchronized Signed-off-by: Eddie Hung <[email protected]> * CounterGenerator to flatten design Signed-off-by: Eddie Hung <[email protected]> * Design.get{Gnd,Vcc}Net() outside of multi-threaded section Signed-off-by: Eddie Hung <[email protected]> * Restore comment Signed-off-by: Eddie Hung <[email protected]> * No less than 100 objects per job Signed-off-by: Eddie Hung <[email protected]> * Fix TestNet Signed-off-by: Eddie Hung <[email protected]> * [TestSiteInst] Add testAddPinDuplicate() Signed-off-by: Eddie Hung <[email protected]> * Refactor Signed-off-by: Eddie Hung <[email protected]> * Restore submodule Signed-off-by: Eddie Hung <[email protected]> * Address review comments Signed-off-by: Eddie Hung <[email protected]> --------- Signed-off-by: Andrew Butt <[email protected]> Signed-off-by: Eddie Hung <[email protected]> Signed-off-by: Chris Lavin <[email protected]> Co-authored-by: Andrew Butt <[email protected]> Co-authored-by: Chris Lavin <[email protected]>
* [VersalClockRouting] VDISTR tree storage map for Versal Signed-off-by: Chris Lavin <[email protected]> * Preliminary v80 support Signed-off-by: Chris Lavin <[email protected]> * Refactoring to use preferred clk root; adds VersalClockTree object Signed-off-by: Chris Lavin <[email protected]> * Update storage format and file for vdistr paths on Versal Signed-off-by: Chris Lavin <[email protected]> * Increasing the search space for clock root column candidates Signed-off-by: Chris Lavin <[email protected]> * Apply suggestions from code review Signed-off-by: Chris Lavin <[email protected]> Signed-off-by: Chris Lavin <[email protected]> * Add an assert Signed-off-by: Chris Lavin <[email protected]> * Adds all Versal devices (except vp1902) Signed-off-by: Chris Lavin <[email protected]> * Adding test to check that Versal distribution template in use Signed-off-by: Chris Lavin <[email protected]> * New data file fixes missing entries Signed-off-by: Chris Lavin <[email protected]> --------- Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
* [TestRWRoute] Initial testSLRCrossingNonTimingDriven for Versal Signed-off-by: Eddie Hung <[email protected]> * [RWRoute] Initial Versal SLR crossing support Signed-off-by: Eddie Hung <[email protected]> * More tests Signed-off-by: Eddie Hung <[email protected]> * [RouteNodeGraph] Dynamic SLL length Signed-off-by: Eddie Hung <[email protected]> * Account for overshooting in Y due to SLLs Signed-off-by: Eddie Hung <[email protected]> * Tidy Signed-off-by: Eddie Hung <[email protected]> * One more test Signed-off-by: Eddie Hung <[email protected]> * Tidy Signed-off-by: Eddie Hung <[email protected]> * Track NODE_SLL_DATA usage Signed-off-by: Eddie Hung <[email protected]> * Fix end tile computation for SLL tiles Signed-off-by: Eddie Hung <[email protected]> * Refactor routethru check Signed-off-by: Eddie Hung <[email protected]> * Comments Signed-off-by: Eddie Hung <[email protected]> * Only check NODE_CLE_BNODE for reaching SLRs Signed-off-by: Eddie Hung <[email protected]> * Make INODEs for inter-SLR connections accessible Allowing INODE -> BOUNCE -> BNODE -> SLL_INPUT Signed-off-by: Eddie Hung <[email protected]> * RWRoute Versal SLR Crossing Test (#1327) * Bump RapidWrightDCP Signed-off-by: Andrew Butt <[email protected]> * Add Versal SLR crossing rwroute test Signed-off-by: Andrew Butt <[email protected]> --------- Signed-off-by: Andrew Butt <[email protected]> * Do not unroute since RWRoute unroutes anyway Signed-off-by: Eddie Hung <[email protected]> * Incorporate fixed DCP Signed-off-by: Chris Lavin <[email protected]> * Fix bad GUI constructor Signed-off-by: Chris Lavin <[email protected]> * Fix PBlockRange XDC parser to handle multiple ranges in same cmd Signed-off-by: Chris Lavin <[email protected]> * Updating submodule RapidWrightDCP Signed-off-by: Chris Lavin <[email protected]> * Tidy up Signed-off-by: Eddie Hung <[email protected]> * Redundant Signed-off-by: Eddie Hung <[email protected]> * Check grandparent instead of regex Signed-off-by: Eddie Hung <[email protected]> * Update comment Signed-off-by: Eddie Hung <[email protected]> * Test that no routethrus are used when terminating at LAG pin for FF Signed-off-by: Eddie Hung <[email protected]> * Apply suggestions from code review Signed-off-by: eddieh-xlnx <[email protected]> --------- Signed-off-by: Eddie Hung <[email protected]> Signed-off-by: Andrew Butt <[email protected]> Signed-off-by: Chris Lavin <[email protected]> Signed-off-by: eddieh-xlnx <[email protected]> Co-authored-by: Andrew Butt <[email protected]> Co-authored-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
* Add ability to constraint InlineFlops to a specific side of the PBlock to improve routability. Also unroute top-level I/O nets that exit the pblock. Signed-off-by: Andrew Butt <[email protected]> * Use regex for port side map Signed-off-by: Andrew Butt <[email protected]> * Address comments Signed-off-by: Andrew Butt <[email protected]> * Update to new getBitBlastedIndices Signed-off-by: Andrew Butt <[email protected]> * Remove unnecessary function calls Signed-off-by: Andrew Butt <[email protected]> * Add test case of unrouteTopLevelNetsThatLeavePBlock Signed-off-by: Andrew Butt <[email protected]> * Remove extra imports Signed-off-by: Andrew Butt <[email protected]> * Add initial removeInlineFlops test Signed-off-by: Andrew Butt <[email protected]> * Test remove inline flops and remove unnecessary code Signed-off-by: Andrew Butt <[email protected]> * Add back pin removal because of the specific case where a flop is in the same slice as a ground source Signed-off-by: Andrew Butt <[email protected]> * Address comments and add new test cases Signed-off-by: Andrew Butt <[email protected]> * Cleanup Signed-off-by: Andrew Butt <[email protected]> * Update based on comment Signed-off-by: Andrew Butt <[email protected]> --------- Signed-off-by: Andrew Butt <[email protected]>
* Add ability to constraint InlineFlops to a specific side of the PBlock to improve routability. Also unroute top-level I/O nets that exit the pblock. Signed-off-by: Andrew Butt <[email protected]> * Automate placement in ArrayBuilder Signed-off-by: Andrew Butt <[email protected]> * Use regex for port side map Signed-off-by: Andrew Butt <[email protected]> * Address comments Signed-off-by: Andrew Butt <[email protected]> * Update to new getBitBlastedIndices Signed-off-by: Andrew Butt <[email protected]> * Remove unnecessary function calls Signed-off-by: Andrew Butt <[email protected]> * Add test case of unrouteTopLevelNetsThatLeavePBlock Signed-off-by: Andrew Butt <[email protected]> * Remove extra imports Signed-off-by: Andrew Butt <[email protected]> * Add initial removeInlineFlops test Signed-off-by: Andrew Butt <[email protected]> * Test remove inline flops and remove unnecessary code Signed-off-by: Andrew Butt <[email protected]> * Add back pin removal because of the specific case where a flop is in the same slice as a ground source Signed-off-by: Andrew Butt <[email protected]> * Add ability to route array builder design Signed-off-by: Andrew Butt <[email protected]> * Remove hardcoded placement constraints Signed-off-by: Andrew Butt <[email protected]> * Handle null case Signed-off-by: Andrew Butt <[email protected]> * Address comments and add new test cases Signed-off-by: Andrew Butt <[email protected]> * Cleanup Signed-off-by: Andrew Butt <[email protected]> * Address comments Signed-off-by: Andrew Butt <[email protected]> --------- Signed-off-by: Andrew Butt <[email protected]>
* Add ability to constraint InlineFlops to a specific side of the PBlock to improve routability. Also unroute top-level I/O nets that exit the pblock. Signed-off-by: Andrew Butt <[email protected]> * Automate placement in ArrayBuilder Signed-off-by: Andrew Butt <[email protected]> * Use regex for port side map Signed-off-by: Andrew Butt <[email protected]> * Address comments Signed-off-by: Andrew Butt <[email protected]> * Update to new getBitBlastedIndices Signed-off-by: Andrew Butt <[email protected]> * Remove unnecessary function calls Signed-off-by: Andrew Butt <[email protected]> * Add test case of unrouteTopLevelNetsThatLeavePBlock Signed-off-by: Andrew Butt <[email protected]> * Remove extra imports Signed-off-by: Andrew Butt <[email protected]> * Add initial removeInlineFlops test Signed-off-by: Andrew Butt <[email protected]> * Test remove inline flops and remove unnecessary code Signed-off-by: Andrew Butt <[email protected]> * Add back pin removal because of the specific case where a flop is in the same slice as a ground source Signed-off-by: Andrew Butt <[email protected]> * Add ability to route array builder design Signed-off-by: Andrew Butt <[email protected]> * Remove hardcoded placement constraints Signed-off-by: Andrew Butt <[email protected]> * Handle null case Signed-off-by: Andrew Butt <[email protected]> * Address comments and add new test cases Signed-off-by: Andrew Butt <[email protected]> * Cleanup Signed-off-by: Andrew Butt <[email protected]> * Start refactoring array builder Signed-off-by: Andrew Butt <[email protected]> * Refactor mostly complete Signed-off-by: Andrew Butt <[email protected]> * Time flop harness creation Signed-off-by: Andrew Butt <[email protected]> * More ArrayBuilder refactoring Signed-off-by: Andrew Butt <[email protected]> * Move main Signed-off-by: Andrew Butt <[email protected]> * Fix array builder failure Signed-off-by: Andrew Butt <[email protected]> * Marge origin/array_builder_placement Signed-off-by: Andrew Butt <[email protected]> * Add javadoc Signed-off-by: Andrew Butt <[email protected]> --------- Signed-off-by: Andrew Butt <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
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