Building a modern computer from first principles. Starting with elementary NAND gates and culminating in a general-purpose computer system capable of running Tetris.
Implementation of fundamental logic gates, building from NAND to create Not, And, Or, Xor, Mux, DMux, and their variants.
What I Learned:
- Logic Gate Universality: How NAND alone can implement any Boolean function
- Hardware Description Language (HDL): Declarative approach to circuit design
- Hierarchical Design: Building complex chips from simpler components
- Bus Notation: Working with multi-bit data paths (16-bit operations)
- Multiplexing/Demultiplexing: Data routing and selection mechanisms
Implemented:
- Basic gates: Not, And, Or, Xor
- 16-bit variants: Not16, And16, Or16
- Multi-way gates: Or8Way
- Multiplexers: Mux, Mux16, Mux4Way16, Mux8Way16
- Demultiplexers: DMux, DMux4Way, DMux8Way
Implementation of arithmetic circuits, from basic adders to a complete Arithmetic Logic Unit (ALU).
What I Learned:
- Binary Addition: Half adder and full adder circuits with carry propagation
- Ripple-Carry Architecture: Chaining adders for multi-bit addition
- Two's Complement Arithmetic: Hardware representation of negative numbers
- ALU Design: Using control bits to configure multiple operations in one chip
- Status Flags: Computing zero (zr) and negative (ng) flags for conditional logic
- Arithmetic Tricks: Implementing subtraction and increment using addition and bit manipulation
Implemented:
- Basic adders: HalfAdder, FullAdder
- 16-bit arithmetic: Add16, Inc16
- ALU: 18 operations controlled by 6 control bits (zx, nx, zy, ny, f, no)
- Arithmetic: 0, 1, -1, x+1, y+1, x-1, y-1, x+y, x-y, y-x
- Logical: x, y, !x, !y, -x, -y, x&y, x|y
Implementation of memory units and sequential logic, from single-bit registers to 16K RAM modules and a program counter.
What I Learned:
- Sequential Logic: Using DFF (Data Flip-Flop) as the primitive for storing state over time
- Feedback Loops: Creating memory by feeding output back to input through a DFF
- Register Design: Building multi-bit registers from 1-bit registers
- Memory Hierarchy: Scaling from single registers to large RAM modules using hierarchical composition
- Address Decoding: Using DMux to route write operations and Mux to route read operations
- Program Counter Logic: Implementing increment, load, and reset operations with priority handling
- Time Abstraction: Understanding the relationship between combinational logic and clock cycles
Implemented:
- Basic sequential: Bit (1-bit register using DFF)
- Multi-bit register: Register (16-bit register)
- Small RAM modules: RAM8, RAM64
- Large RAM modules: RAM512, RAM4K, RAM16K
- Program Counter: PC (with increment, load, and reset capabilities)