Skip to content

Improvements to formatting, documentation and coprogen #295

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom
Closed
hfthra wants to merge 87 commits into from
Closed

Improvements to formatting, documentation and coprogen #295

hfthra wants to merge 87 commits into from

Conversation

@hfthra
Copy link

@hfthra hfthra commented Jan 19, 2026

Improvements to comments and formatting, changing coprogen to RVCoprocessorGenerator and changes to the documentation

Joonari added 30 commits March 14, 2025 16:53
@Joonari
Add register file generator (RFGen)
bddc021 
Can generate netlist block and RF ports now.
@Joonari
tcetest_bypass.sh: Add error message when itrace not correct
05b40ec
@Joonari
FUGen: Fix extra parenthesis and signal default value
916e020
@Joonari
Fix filename used in LSU RTL generation
78afcd0
@Joonari
FUGen: Fix verilog issues
d7ebb04 
Signal formatting was missing a bracket when sign extending, and
signal load_data_32b was not declared
@Joonari
Add verilog testbench template for the new TB generator
2b6c723
@Joonari
FUGen: Use don't care ('-') as signal init value only when specified
0baec96 
Add --dont-care-init option to generateprocessor to initialize signals as ('-').
Don't care values cause issues in ASIC synthesis tools, so use '0'
as the default init value.
@Joonari
WIP
f336828
@Joonari
Remove 'unique' from verilog case statements (it's a systemverilog fe…
94d907a 
…ature)
@Joonari
Fix issues with verilog parameter definition
dda665b 
Change order of verilog include files containing parameter declarations,
and add IMEMDATAWIDTH parameter to verilog package file
@Joonari
Remove debug prints
9ba61ce
@Joonari
Fix SinglePortSSRAMBlock port width.
6bc6e84 
Module's 'd' port was initialized with zeroes. Verilog replication operator does not allow
using a parameter of the same block to do this.
@Joonari
Fix boolean parameter value in verilog HW generation
92028a1
@Joonari
Add clkgen.v
2e9fc43
@Joonari
Fix for loop in SRAM verilog model
61e8375
@Joonari
Fix parameters in SRAM verilog model
c6e6126
@Joonari
Fix verilog testbench template
f44a2a7
@Joonari
Add lsu_registers.v to HDB in generate.py
240886b
@Joonari
Add missing reset value for rdata_r in lsu_registers.vhdl
84c6c33
@Joonari
Add parameter default values
ad2038d
@Joonari
Fix port name in instantiated verilog modules
8f64814
@Joonari
Change verilog standard from 2001 to 2012 in iverilog compile script
619dea4
@Joonari
Remove debug prints
bd6ba62
@Joonari
Multiple fixes to verilog netlist writer
f4518cc
@Joonari
Fix issue with execution_count_reg
3901369
@Joonari
Compile files as SystemVerilog when using modelsim
ffe0ef8
@Joonari
Remove verilog timescale definitions + TB fixes
4340611
@Joonari
FUGen: Fix constant value assignments
be64019
@Joonari
Remove clkgen.v from instantiated files. Clk is generated directly in…
eb36d5e 
… TB now.
@Joonari
Parameter package fixes + TB initial clk value fix to match VHDL version
85399f2
Joonari and others added 25 commits March 14, 2025 16:53
@Joonari
Add test generator (TeGe)
b85ff06
@Joonari
Remove file suffix from an operation name in generate_base32.hdb
c581faa
@Joonari
Update testrunner.py for python 3 instead of 2
8f5f591
@hfthra
coprocessor generator
4d61b3f
@hfthra
Formatting improved and changes to the license statements
2f6f7b0
@hfthra
Added SV template files, changes in RISCV customOps, Other corrections
c949eea
@hfthra
changing licenses on SV templates to MIT
3983a39
@Joonari
Install iverilog in github workflow
bf22f27
@Joonari
Reduce mem sizes in ADFs to avoid excessive simulation memory usage
a77aaf6
@hfthra
change wire type to reg in HDL verilog generation
873b4a4
@hfthra
added test scripts and files for coprocessorgenerator, fixes
0a64783
@hfthra
changing TUT to Tampere University
9fc6ada
@hfthra
Added coprocessor generation to the manual
1fbae5b
@hfthra
Merge branch 'fugen-verilog-fixes' into coprocessor-generator
2fcc1fb
@hfthra
removing latch behavior
cd4e989
@hfthra
adding a missing definition
ba2cb36
@hfthra
Modify coprocesser generation tutorial guide and script
00a634a
@hfthra
adding paths in the RoCC config to the coprocessor tutorial script
31b6d7d
@hfthra
add register read to cvxif coprocessor template, refine copro tour sc…
17077af 
…ript and tutorial
@hfthra
adding tested cva6 and chipyard versions to the tutorial
c3cd7d1
@hfthra
Formatting corrections
aa278fb
@hfthra
adding license details of the scala files taken from Chipyard
abd8d2a
@hfthra
changing CoproGen to RVCoprocessorGenerator
058dfb1
@hfthra
changes to the coprocessor generation section in the doc
713c1c5
@hfthra
Merge branch 'fugen-verilog-fixes' into coprocessor-generator
63bcfab
@pjaaskel
Copy link
Contributor

pjaaskel commented Jan 19, 2026

How is this related to #279 and does it include its changes. @Joonari had it nicely squashed to 3 commits.

@hfthra
Copy link
Author

hfthra commented Jan 19, 2026

Yes, this includes the changes

@pjaaskel
Copy link
Contributor

pjaaskel commented Jan 19, 2026

Yes, this includes the changes

...yet has 87 commits.

@hfthra
Copy link
Author

hfthra commented Jan 20, 2026

created #296 with clean commits for the same, so closing this PR.

@hfthra hfthra closed this Jan 20, 2026
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Reviewers

No reviews

Assignees

No one assigned

Labels

None yet

Projects

None yet

Milestone

No milestone

Development

Successfully merging this pull request may close these issues.

4 participants

@hfthra @pjaaskel @Joonari @karihepola