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Summary:
This microbenchmark battery aims to study the CPUs front-end performance. A few notable features:

  • We can identify branch target buffer length
  • We can identify call prediction buffer length
  • We can measure instruction fetch throughput when code sits at different cache levels
  • We can measure the behavior of the CPU in the context of many iTLB misses

Differential Revision: D89094585

Summary:
This microbenchmark battery aims to study the CPUs front-end performance. A few notable features:

- We can identify branch target buffer length
- We can identify call prediction buffer length
- We can measure instruction fetch throughput when code sits at different cache levels
- We can measure the behavior of the CPU in the context of many iTLB misses

Differential Revision: D89094585
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meta-codesync bot commented Dec 16, 2025

@valentinandrei has exported this pull request. If you are a Meta employee, you can view the originating Diff in D89094585.

@meta-cla meta-cla bot added the CLA Signed This label is managed by the Facebook bot. Authors need to sign the CLA before a PR can be reviewed. label Dec 16, 2025
meta-codesync bot pushed a commit that referenced this pull request Dec 16, 2025
Summary:
Pull Request resolved: #343

This microbenchmark battery aims to study the CPUs front-end performance. A few notable features:

- We can identify branch target buffer length
- We can identify call prediction buffer length
- We can measure instruction fetch throughput when code sits at different cache levels
- We can measure the behavior of the CPU in the context of many iTLB misses

Reviewed By: excelle08

Differential Revision: D89094585

fbshipit-source-id: 2baa94e3a9beff446f83a769a3898ba9bb2b2b23
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2 participants