[LLVM Pulldown] Bump to rev aba8ebbda0912ef2037668aaa48cfbe59991576f

build_tools/llvm_version.txt

@@ -1 +1 @@
-d041d5d4e07ba0eddd5120efd66520b3984a2b9b
+aba8ebbda0912ef2037668aaa48cfbe59991576f

build_tools/patches/0004-Add-serialization-and-de-serialization-support-for-s.patch

@@ -65,5 +65,5 @@ index c879a2b3e020..0ccaa72d319b 100644
      // For unit attributes and decoration attributes, the args list
      // has no values so we do nothing.
      if (isa<UnitAttr, DecorationAttr>(attr))
--- 
+--
 2.34.1

build_tools/patches/0008-xegpu-temporary-downstream-defintion-changes-and-vec.patch

@@ -1,37 +1,37 @@
-From e77e0d6492be15747db4577305de18dcad87b92b Mon Sep 17 00:00:00 2001
+From d648c9d2403baac3c757157ab8bfd72111c5fa48 Mon Sep 17 00:00:00 2001
 From: Garra1980 <[email protected]>
-Date: Mon, 1 Dec 2025 19:16:15 +0100
+Date: Wed, 10 Dec 2025 16:52:10 +0100
 Subject: [PATCH] xegpu temporary downstream defintion changes and vec
 
 ---
  mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td | 6 ++++++
- mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp         | 9 ++++++---
- 2 files changed, 12 insertions(+), 3 deletions(-)
+ mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp         | 8 +++++---
+ 2 files changed, 11 insertions(+), 3 deletions(-)
 
 diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
-index d93ffb70881b..6e8c5884bfe6 100644
+index b54d620c3c0c..3d9cc4a071bc 100644
 --- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
 +++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
-@@ -402,6 +402,7 @@ def XeGPU_LoadNdOp : XeGPU_Op<"load_nd", [
+@@ -403,6 +403,7 @@ def XeGPU_LoadNdOp : XeGPU_Op<"load_nd", [
                         OptionalAttr<DenseI64ArrayAttr>: $const_offsets,
                         OptionalAttr<UnitAttr>: $packed,
                         OptionalAttr<DenseI64ArrayAttr>: $transpose,
 +                       OptionalAttr<I32Attr>: $transpose_bit_width,
                         OptionalAttr<XeGPU_CacheHintAttr>: $l1_hint,
                         OptionalAttr<XeGPU_CacheHintAttr>: $l2_hint,
-                        OptionalAttr<XeGPU_CacheHintAttr>: $l3_hint, 
-@@ -1619,4 +1620,9 @@ def XeGPU_StoreMatrixOp: XeGPU_Op<"store_matrix", [MemoryEffects<[MemWrite]>,
+                        OptionalAttr<XeGPU_CacheHintAttr>: $l3_hint,
+@@ -1622,4 +1623,9 @@ def XeGPU_StoreMatrixOp: XeGPU_Op<"store_matrix", [MemoryEffects<[MemWrite]>,
    let hasVerifier = 1;
  }
- 
+
 +def XeGPU_CompileHintOp : XeGPU_Op<"compile_hint", []> {
 +  let summary = "prevents the compiler from scheduling.";
 +  let assemblyFormat = [{ attr-dict }];
 +}
 +
  #endif // MLIR_DIALECT_XEGPU_IR_XEGPUOPS_TD
 diff --git a/mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp b/mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
-index 8cb666298c95..ff7f1afeb4af 100644
+index 91ba07a8e025..6ebcd3818bb6 100644
 --- a/mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
 +++ b/mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
 @@ -71,6 +71,7 @@ static bool isWriteHintOrNone(const CachePolicyAttr &attr) {
@@ -41,36 +41,34 @@ index 8cb666298c95..ff7f1afeb4af 100644
 +         kind == CachePolicy::STREAMING ||
           kind == CachePolicy::WRITE_BACK || kind == CachePolicy::WRITE_THROUGH;
  }
- 
-@@ -518,7 +519,8 @@ void LoadNdOp::build(OpBuilder &builder, OperationState &state, Type retType,
+
+@@ -519,7 +520,8 @@ void LoadNdOp::build(OpBuilder &builder, OperationState &state, Type retType,
                       xegpu::CachePolicyAttr l3_hint) {
- 
+
    return build(builder, state, retType, tensorDesc, ValueRange(),
 -               DenseI64ArrayAttr(), packed, transpose, l1_hint, l2_hint,
 +               DenseI64ArrayAttr(), packed, transpose, nullptr, /*transpose_bit_width*/
 +               l1_hint, l2_hint,
                 l3_hint, /*anchor_layout=*/nullptr);
  }
- 
-@@ -535,7 +537,8 @@ void LoadNdOp::build(OpBuilder &builder, OperationState &state, Type retType,
+
+@@ -537,7 +539,7 @@ void LoadNdOp::build(OpBuilder &builder, OperationState &state, Type retType,
    auto staticOffsetsAttr = builder.getDenseI64ArrayAttr(staticOffsets);
- 
+
    build(builder, state, retType, tensorDesc, dynamicOffsets, staticOffsetsAttr,
 -        packed, transpose, l1_hint, l2_hint, l3_hint,
-+        packed, transpose, nullptr, /*transpose_bit_width*/
-+        l1_hint, l2_hint, l3_hint,
-         /*anchor_layout=*/nullptr);
++        packed, transpose, nullptr /*transpose_bit_width*/, l1_hint, l2_hint, l3_hint,
+         /*anchor_layout=*/layout);
  }
- 
-@@ -598,7 +601,7 @@ LogicalResult LoadNdOp::verify() {
+
+@@ -600,7 +602,7 @@ LogicalResult LoadNdOp::verify() {
        mlir::emitWarning(getLoc()) << "Invalid transpose attr. It is ignored.";
    }
- 
+
 -  if (getPacked()) {
 +  if (getPacked() || getTransposeBitWidth() == 32) {
      if (tdescTy.getRank() == 2) {
        const int axis = 0;
        auto vnni_factor = valueShape.back();
--- 
+--
 2.34.1
-

build_tools/patches/relaxing_xegpu-propagation.patch

@@ -29,6 +29,5 @@ index 6b3ba5a5981c..ecd6a3358f4a 100644
    return llvm::map_to_vector(storage.getEffectiveLaneDataAsInt(),
                               [](int64_t val) { return static_cast<int>(val); });
  }
--- 
+--
 2.34.1
-

lib/Conversion/XeTileToXeGPU/XeTileToXeGPU.cpp

@@ -492,9 +492,10 @@ class LoadOpPattern : public OpConversionPattern<xetile::LoadTileOp> {
     auto packAttr = UnitAttr();
     auto transAttr = DenseI64ArrayAttr();
     auto bitWidthAttr = IntegerAttr();
-    auto ldOp = xegpu::LoadNdOp::create(
-        rewriter, loc, vecTy, adaptor.getTile(), ValueRange(),
-        DenseI64ArrayAttr(), packAttr, transAttr, bitWidthAttr, L1, L2, L3, nullptr);
+    auto ldOp =
+        xegpu::LoadNdOp::create(rewriter, loc, vecTy, adaptor.getTile(),
+                                ValueRange(), DenseI64ArrayAttr(), packAttr,
+                                transAttr, bitWidthAttr, L1, L2, L3, nullptr);
 
     llvm::SmallVector<Value> results({ldOp.getResult()});
     if (memSpace == xegpu::MemorySpace::SLM) {
@@ -638,8 +639,9 @@ class AtomicRMWOpPattern : public OpConversionPattern<xetile::AtomicRMWOp> {
     auto maskAttr = DenseElementsAttr::get(maskTy, maskValues);
     Value mask = arith::ConstantOp::create(rewriter, loc, maskTy, maskAttr);
     value = vector::ShapeCastOp::create(rewriter, loc, valTy, value);
-    auto rmwOp = xegpu::AtomicRMWOp::create(rewriter, loc, valTy, op.getKind(),
-                                            adaptor.getTile(), mask, value, nullptr);
+    auto rmwOp =
+        xegpu::AtomicRMWOp::create(rewriter, loc, valTy, op.getKind(),
+                                   adaptor.getTile(), mask, value, nullptr);
     auto v = vector::ShapeCastOp::create(rewriter, loc, op.getType(), rmwOp);
     rewriter.replaceOp(op, v);
     return success();
@@ -654,7 +656,7 @@ class MMAOpPattern : public OpConversionPattern<xetile::TileMMAOp> {
   matchAndRewrite(xetile::TileMMAOp op, OpAdaptor adaptor,
                   ConversionPatternRewriter &rewriter) const override {
     rewriter.replaceOpWithNewOp<xegpu::DpasOp>(op, op.getType(), adaptor.getA(),
-                                               adaptor.getB(), adaptor.getC(), 
+                                               adaptor.getB(), adaptor.getC(),
                                                nullptr, nullptr, nullptr);
     return success();
   }

lib/Transforms/MaterializeMatrixOp.cpp

@@ -48,7 +48,8 @@ class CreateMemDescOpPattern final
   LogicalResult
   matchAndRewrite(xegpu::CreateMemDescOp op, OpAdaptor adaptor,
                   ConversionPatternRewriter &rewriter) const override {
-    TypedValue<MemRefType> src = dyn_cast<TypedValue<MemRefType>>(op.getSource());
+    TypedValue<MemRefType> src =
+        dyn_cast<TypedValue<MemRefType>>(op.getSource());
     MemDescType resTy = op.getMemDesc().getType();
     auto *converter = getTypeConverter();
     MemRefType newResTy = converter->convertType<MemRefType>(resTy);