[doc] Clarify usage of data independent timing & branch prediction

doc/03_reference/instruction_fetch.rst

@@ -26,6 +26,8 @@ The interfaces of the icache module are the same as the prefetch buffer with two
 Firstly, a signal to enable the cache which is driven from a custom CSR.
 Secondly a signal to the flush the cache which is set every time a ``fence.i`` instruction is executed.
 
+.. _branch-prediction:
+
 Branch Prediction
 -----------------
 

doc/03_reference/security.rst

@@ -36,6 +36,8 @@ Software that has need of data independent timing may wish to disable the instru
 The instruction cache is controlled by the **icache_enable** bit in the **cpuctrl** register.
 Precise details of fetch timing will depend upon the memory system Ibex is connected to.
 
+If data independent timing is needed for branches, turn off the branch prediction feature as it is :ref:`experimental<branch-prediction>`.
+
 Dummy Instruction Insertion
 ---------------------------