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Draft: Add LLC bypass region for Carfield #176

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994bef7
pkg: Add LLC bypass memory region at 0x20000000
CyrilKoe Jan 5, 2025
04c05a8
bender: Update axi_llc with SPM debug
CyrilKoe Jan 5, 2025
0071e68
sw: Add LLC functions
CyrilKoe Jan 5, 2025
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2 changes: 1 addition & 1 deletion Bender.lock
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Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ packages:
- common_verification
- tech_cells_generic
axi_llc:
revision: 7d7fc1349d4915a657de535a491bc26fbf0d2cfa
revision: 7c681312ae1eb912052de98ddaf5d19e1c2b76ff
version: null
source:
Git: https://github.com/pulp-platform/axi_llc.git
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2 changes: 1 addition & 1 deletion Bender.yml
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Expand Up @@ -14,7 +14,7 @@ package:
dependencies:
apb_uart: { git: "https://github.com/pulp-platform/apb_uart.git", version: 0.2.1 }
axi: { git: "https://github.com/pulp-platform/axi", rev: 4fb5a02 }
axi_llc: { git: "https://github.com/pulp-platform/axi_llc", rev: 7d7fc13 }
axi_llc: { git: "https://github.com/pulp-platform/axi_llc", rev: 7c68131 } # branch: llc_partition_opt
axi_riscv_atomics: { git: "https://github.com/pulp-platform/axi_riscv_atomics.git", version: 0.8.1 }
axi_rt: { git: "https://github.com/pulp-platform/axi_rt.git", version: 0.0.0-alpha.4 }
axi_vga: { git: "https://github.com/pulp-platform/axi_vga.git", version: 0.1.1 }
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6 changes: 6 additions & 0 deletions hw/cheshire_pkg.sv
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Expand Up @@ -162,6 +162,8 @@ package cheshire_pkg;
bit LlcOutConnect;
doub_bt LlcOutRegionStart;
doub_bt LlcOutRegionEnd;
doub_bt LlcBypassRegionStart;
doub_bt LlcBypassRegionEnd;
dw_bt LlcUserMsb;
dw_bt LlcUserLsb;
// Parameters for VGA
Expand Down Expand Up @@ -348,6 +350,8 @@ package cheshire_pkg;
// own Xbar output with the specified region iff it is connected.
if (cfg.LlcOutConnect) begin i++; r++; ret.llc = i;
ret.map[r] = '{i, cfg.LlcOutRegionStart, cfg.LlcOutRegionEnd}; end
if (cfg.LlcOutConnect) begin r++;
ret.map[r] = '{i, cfg.LlcBypassRegionStart, cfg.LlcBypassRegionEnd}; end
// We can only internally map the SPM region if an LLC exists.
// Otherwise, we assume external ports map and back the SPM region.
// We map both the cached and uncached regions.
Expand Down Expand Up @@ -589,6 +593,8 @@ package cheshire_pkg;
LlcOutConnect : 1,
LlcOutRegionStart : 'h8000_0000,
LlcOutRegionEnd : 'h1_0000_0000,
LlcBypassRegionStart : 'h2_8000_0000,
LlcBypassRegionEnd : 'h3_0000_0000,
LlcUserMsb : 0,
LlcUserLsb : 0,
// LLC Partitioning
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13 changes: 13 additions & 0 deletions sw/include/dif/axi_llc.h
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@@ -0,0 +1,13 @@
// Copyright 2022 ETH Zurich and University of Bologna.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Cyril Koenig <[email protected]>

#pragma once

void llc_enable();

void llc_flush();

void llc_disable();
38 changes: 38 additions & 0 deletions sw/lib/dif/llc.c
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@@ -0,0 +1,38 @@
// Copyright 2022 ETH Zurich and University of Bologna.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Cyril Koenig <[email protected]>

#include "dif/axi_llc.h"
#include "regs/axi_llc.h"
#include "util.h"
#include "params.h"

void llc_enable() {
*reg32(&__base_llc, AXI_LLC_CFG_SPM_LOW_REG_OFFSET ) = 0x00000000;
*reg32(&__base_llc, AXI_LLC_CFG_SPM_HIGH_REG_OFFSET) = 0x00000000;
fence();
*reg32(&__base_llc, AXI_LLC_COMMIT_CFG_REG_OFFSET) = 0x1;
fence();
}

void llc_flush() {
*reg32(&__base_llc, AXI_LLC_CFG_FLUSH_LOW_REG_OFFSET ) = 0xffffffff;
*reg32(&__base_llc, AXI_LLC_CFG_FLUSH_HIGH_REG_OFFSET) = 0xffffffff;
fence();
*reg32(&__base_llc, AXI_LLC_COMMIT_CFG_REG_OFFSET) = 0x1;
fence();
while(*reg32(&__base_llc, AXI_LLC_CFG_FLUSH_LOW_REG_OFFSET) != 0);
while(*reg32(&__base_llc, AXI_LLC_CFG_FLUSH_HIGH_REG_OFFSET) != 0);
}

void llc_disable() {
*reg32(&__base_llc, AXI_LLC_CFG_SPM_LOW_REG_OFFSET ) = 0xffffffff;
*reg32(&__base_llc, AXI_LLC_CFG_SPM_HIGH_REG_OFFSET) = 0xffffffff;
*reg32(&__base_llc, AXI_LLC_CFG_FLUSH_LOW_REG_OFFSET ) = 0xffffffff;
*reg32(&__base_llc, AXI_LLC_CFG_FLUSH_HIGH_REG_OFFSET) = 0xffffffff;
fence();
*reg32(&__base_llc, AXI_LLC_COMMIT_CFG_REG_OFFSET) = 0x1;
fence();
}
2 changes: 2 additions & 0 deletions target/xilinx/src/cheshire_top_xilinx.sv
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Expand Up @@ -123,6 +123,8 @@ module cheshire_top_xilinx
LlcOutConnect : 1,
LlcOutRegionStart : 'h8000_0000,
LlcOutRegionEnd : 'h1_0000_0000,
LlcBypassRegionStart : 'h2_8000_0000,
LlcBypassRegionEnd : 'h3_0000_0000,
LlcUserMsb : 0,
LlcUserLsb : 0,
// LLC partitioning
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