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@fischeti fischeti commented Nov 30, 2025

Integrates new clint version with systemRDL registers and an APB interface.

TODO:

  • Merge Convert registers to RDL, remove templating, convert to APB clint#5 and point clint to new release
  • Fix Gitlab CI: At the moment, the compilation fails because the installed peakrdl-regblock package is too old, which omits parameter definition in the generated packages.
  • Gitlab CI: fix ERROR: Cannot start server on port 3042: already in use. errors during FPGA boot jobs

@fischeti fischeti marked this pull request as ready for review November 30, 2025 17:30
@fischeti fischeti requested a review from paulsc96 December 1, 2025 09:13
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paulsc96 commented Dec 2, 2025

I updated peakrdl-regblock and the build works in CI now.

I have no objections to this PR in principle. The question is if we want to coordinate this with other migrations to SystemRDL (and, with it, a migration from regbus to APB peripheral interconnect?) or merge it as is. The additional adapter is fine for a first approach, but I'd like to see a more principled integration in the next release.

Or, that's what I would say if the next release was my problem. But it is very likely not. So if you manage to identify a responsible maintainer for this repo, you can decide the next steps with them.

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fischeti commented Dec 4, 2025

Replacing the Regbus with an APB bus is definitely the end goal here.

I also don't like the converters too much, and migrating everything at once to SystemRDL would be nicer. However, I think this endeavour has a better chance of success when if it is approached step by step. First migrating all dependencies and then Cheshire itself, which would get rid of all the reg2apb converters again.

For me both ways would be fine. I will check with possible future maintainers first, as you said.

@fischeti fischeti requested a review from creinwar December 5, 2025 08:55
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3 participants