@@ -67,7 +67,7 @@ package chimera_pkg;
6767 // -------------------------------
6868 // | External Register Interface |
6969 // -------------------------------
70- localparam bit SnitchBootROM = 1 ;
70+ localparam bit SnitchBootROM = `ifdef TARGET_SNITCH_CLUSTER 1 `else 0 `endif ;
7171 localparam bit TopLevelCfgRegs = 1 ;
7272 localparam bit ExtCfgRegs = 1 ;
7373 localparam bit HyperCfgRegs = 1 ;
@@ -79,23 +79,27 @@ package chimera_pkg;
7979 localparam doub_bt SnitchBootROMRegionStart = 64'h3000_0000 ;
8080 localparam doub_bt SnitchBootROMRegionEnd = 64'h3000_1000 ;
8181
82- localparam byte_bt TopLevelCfgRegsIdx = 8'h1 ;
82+ localparam byte_bt TopLevelCfgRegsIdx = SnitchBootROM ;
8383 localparam doub_bt TopLevelCfgRegsRegionStart = 64'h3000_1000 ;
8484 localparam doub_bt TopLevelCfgRegsRegionEnd = 64'h3000_2000 ;
8585
8686 // External configuration registers: PADs, FLLs, PMU Controller
87- localparam byte_bt ExtCfgRegsIdx = 8'h2 ;
87+ localparam byte_bt ExtCfgRegsIdx = SnitchBootROM + TopLevelCfgRegs ;
8888 localparam doub_bt ExtCfgRegsRegionStart = 64'h3000_2000 ;
8989 localparam doub_bt ExtCfgRegsRegionEnd = 64'h3000_5000 ;
9090
9191 // Hyperbus configuration registers: HyperBus
92- localparam byte_bt HyperCfgRegsIdx = 8'h3 ;
92+ localparam byte_bt HyperCfgRegsIdx = SnitchBootROM + TopLevelCfgRegs + ExtCfgRegs ;
9393 localparam doub_bt HyperCfgRegsRegionStart = 64'h3000_5000 ;
9494 localparam doub_bt HyperCfgRegsRegionEnd = 64'h3000_6000 ;
9595
9696 // --------------------------
9797 // | External AXI ports |
9898 // --------------------------
99+ localparam bit MemoryIsland = 1'b1 ;
100+ localparam bit Hyperbus = 1'b1 ;
101+
102+ localparam int AxiExtNumSlv = ExtClusters + MemoryIsland + Hyperbus;
99103
100104 // Cluster domain
101105 localparam byte_bt [iomsb (ExtClusters): 0 ] ClusterIdx = { 8'h4 , 8'h3 , 8'h2 , 8'h1 , 8'h0 } ;
@@ -110,7 +114,7 @@ package chimera_pkg;
110114 localparam int ClusterDataWidth = 64 ;
111115
112116 // Memory Island
113- localparam byte_bt MemIslandIdx = ClusterIdx[ ExtClusters- 1 ] + 1 ;
117+ localparam byte_bt MemIslandIdx = ExtClusters;
114118 localparam doub_bt MemIslRegionStart = 64'h4800_0000 ;
115119 localparam doub_bt MemIslRegionEnd = 64'h4804_0000 ;
116120
@@ -122,7 +126,7 @@ package chimera_pkg;
122126 localparam shrt_bt MemIslWordsPerBank = 1024 ;
123127
124128 // Hyperbus
125- localparam byte_bt HyperbusIdx = MemIslandIdx + 1 ;
129+ localparam byte_bt HyperbusIdx = ExtClusters + MemoryIsland ;
126130 localparam doub_bt HyperbusRegionStart = 64'h5000_0000 ;
127131 // TODO(smazzola): Correct size of HyperRAM?
128132 localparam doub_bt HyperbusRegionEnd = HyperbusRegionStart + 64'h1000_0000 ;
@@ -139,8 +143,6 @@ package chimera_pkg;
139143
140144 function automatic chimera_cfg_t gen_chimera_cfg ();
141145 localparam int AddrWidth = DefaultCfg.AddrWidth;
142- localparam int MemoryIsland = 1 ;
143- localparam int Hyperbus = 1 ;
144146
145147 chimera_cfg_t chimera_cfg;
146148 cheshire_cfg_t cfg = DefaultCfg;
@@ -168,8 +170,8 @@ package chimera_pkg;
168170
169171 // SCHEREMO: Two ports for each cluster: one to convert stray wides, one for the original narrow
170172 cfg.AxiExtNumMst = ExtClusters + $countones (ChimeraClusterCfg.hasWideMasterPort);
171- cfg.AxiExtNumSlv = ExtClusters + MemoryIsland + Hyperbus ;
172- cfg.AxiExtNumRules = ExtClusters + MemoryIsland + Hyperbus ;
173+ cfg.AxiExtNumSlv = AxiExtNumSlv ;
174+ cfg.AxiExtNumRules = AxiExtNumSlv ;
173175
174176 cfg.AxiExtRegionIdx = { HyperbusIdx, MemIslandIdx, ClusterIdx} ;
175177 cfg.AxiExtRegionStart = { HyperbusRegionStart, MemIslRegionStart, ClusterRegionStart} ;
@@ -178,15 +180,23 @@ package chimera_pkg;
178180 // REG CFG
179181 cfg.RegExtNumSlv = ExtRegNum;
180182 cfg.RegExtNumRules = ExtRegNum;
181- cfg.RegExtRegionIdx = { HyperCfgRegsIdx, ExtCfgRegsIdx, TopLevelCfgRegsIdx, SnitchBootROMIdx} ;
183+ cfg.RegExtRegionIdx = {
184+ HyperCfgRegsIdx,
185+ ExtCfgRegsIdx,
186+ TopLevelCfgRegsIdx
187+ `ifdef TARGET_SNITCH_CLUSTER , SnitchBootROMIdx `endif
188+ } ;
182189 cfg.RegExtRegionStart = {
183190 HyperCfgRegsRegionStart,
184191 ExtCfgRegsRegionStart,
185- TopLevelCfgRegsRegionStart,
186- SnitchBootROMRegionStart
192+ TopLevelCfgRegsRegionStart
193+ `ifdef TARGET_SNITCH_CLUSTER , SnitchBootROMRegionStart `endif
187194 } ;
188195 cfg.RegExtRegionEnd = {
189- HyperCfgRegsRegionEnd, ExtCfgRegsRegionEnd, TopLevelCfgRegsRegionEnd, SnitchBootROMRegionEnd
196+ HyperCfgRegsRegionEnd,
197+ ExtCfgRegsRegionEnd,
198+ TopLevelCfgRegsRegionEnd
199+ `ifdef TARGET_SNITCH_CLUSTER , SnitchBootROMRegionEnd `endif
190200 } ;
191201
192202 // ACCEL HART/IRQ CFG
@@ -279,7 +289,6 @@ package chimera_pkg;
279289 gen_chimera_cfg () // 0: Default configuration
280290 } ;
281291
282-
283292 localparam int unsigned RegDataWidth = 32 ;
284293 localparam type addr_t = logic [ChimeraCfg[0 ].ChsCfg.AddrWidth- 1 : 0 ];
285294 localparam type data_t = logic [RegDataWidth- 1 : 0 ];
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