tree: Introduce SystemRDL support

.github/workflows/lint.yml

@@ -15,7 +15,7 @@ jobs:
     steps:
     -
       name: Checkout
-      uses: actions/checkout@v3
+      uses: actions/checkout@v4
     -
       name: Check license
       uses: pulp-platform/pulp-actions/lint-license@v2
@@ -35,7 +35,7 @@ jobs:
     steps:
     -
       name: Checkout
-      uses: actions/checkout@v3
+      uses: actions/checkout@v4
     -
       name: Run Verible
       uses: chipsalliance/verible-linter-action@main
@@ -45,11 +45,12 @@ jobs:
         github_token: ${{ secrets.GITHUB_TOKEN }}
         fail_on_error: true
         reviewdog_reporter: github-check
+        exclude_paths: hw/rdl
 
   lint-sv-format:
     runs-on: ubuntu-latest
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
         with:
           ref: ${{ github.event.pull_request.head.sha }}
       - name: Run Verible formatter action
@@ -68,7 +69,7 @@ jobs:
     steps:
     -
       name: Checkout
-      uses: actions/checkout@v3
+      uses: actions/checkout@v4
     -
       name: Run Clang-format
       uses: DoozyX/[email protected]

Bender.yml

@@ -31,8 +31,8 @@ workspace:
 sources:
   # Level 0
   - hw/chimera_pkg.sv
-  - hw/regs/chimera_reg_pkg.sv
-  - hw/regs/chimera_reg_top.sv
+  - hw/rdl/chimera_reg_pkg.sv
+  - hw/rdl/chimera_reg_top.sv
   - hw/bootrom/snitch/snitch_bootrom.sv
   - hw/narrow_adapter.sv
   - hw/chimera_cluster_adapter.sv

Makefile

@@ -9,6 +9,7 @@ CHIM_ROOT ?= $(shell pwd)
 # Tooling
 BENDER                 ?= bender -d $(CHIM_ROOT)
 VERIBLE_VERILOG_FORMAT ?= $(CHIM_UTILS_DIR)/verible-verilog/verible-verilog-format
+PEAKRDL                ?= peakrdl
 
 # Set dependency paths only if dependencies have already been cloned
 # This avoids running `bender checkout` at every make command
@@ -62,4 +63,5 @@ help:
 	@echo -e ""
 	@echo -e "Software:"
 	@echo -e "${Green}chim-sw             ${Black}Compile all software tests"
+	@echo -e "${Green}chimera-addrmap     ${Black}Regenerate c-header for SoC address map"
 	@echo -e ""

chimera.mk

@@ -5,7 +5,7 @@
 # Moritz Scherer <[email protected]>
 # Lorenzo Leone <[email protected]>
 
-
+NUMCLUSTERS ?= 5
 CLINTCORES = 46
 PLICCORES = 92
 PLIC_NUM_INTRS = 92
@@ -56,12 +56,19 @@ $(CHIM_ROOT)/hw/bootrom/snitch/snitch_bootrom.bin: $(CHIM_ROOT)/hw/bootrom/snitc
 $(CHIM_ROOT)/hw/bootrom/snitch/snitch_bootrom.sv: $(CHIM_ROOT)/hw/bootrom/snitch/snitch_bootrom.bin $(CHS_ROOT)/util/gen_bootrom.py
 	$(CHS_ROOT)/util/gen_bootrom.py --sv-module snitch_bootrom $< > $@
 
-.PHONY: regenerate_soc_regs
-regenerate_soc_regs: $(CHIM_ROOT)/hw/regs/chimera_reg_pkg.sv $(CHIM_ROOT)/hw/regs/chimera_reg_top.sv $(CHIM_SW_DIR)/include/regs/soc_ctrl.h $(CHIM_HW_DIR)/regs/pcr.md
+#############
+# SystemRDL #
+#############
+CHIM_RDL_ALL += $(CHIM_ROOT)/hw/rdl/chimera.rdl
+CHIM_RDL_ALL += $(CHIM_ROOT)/hw/rdl/snitch_cluster.rdl
+CHIM_RDL_ALL += $(CHIM_ROOT)/hw/rdl/cheshire_host.rdl
+CHIM_RDL_ALL += $(CHIM_ROOT)/hw/rdl/chimera_regs.rdl
 
-.PHONY: $(CHIM_ROOT)/hw/regs/chimera_reg_pkg.sv hw/regs/chimera_reg_top.sv
-$(CHIM_ROOT)/hw/regs/chimera_reg_pkg.sv $(CHIM_ROOT)/hw/regs/chimera_reg_top.sv: $(CHIM_ROOT)/hw/regs/chimera_regs.hjson
-	python $(CHIM_ROOT)/utils/reggen/regtool.py -r $< --outdir $(dir $@)
+.PHONY: regenerate_soc_regs
+regenerate_soc_regs: $(CHIM_ROOT)/hw/rdl/chimera_reg_top.sv $(CHIM_ROOT)/hw/rdl/chimera_reg_pkg.sv
+$(CHIM_ROOT)/hw/rdl/chimera_reg_top.sv $(CHIM_ROOT)/hw/rdl/chimera_reg_pkg.sv: $(CHIM_ROOT)/hw/rdl/chimera_regs.rdl
+	$(PEAKRDL) regblock $< -o $(CHIM_ROOT)/hw/rdl --cpuif apb4-flat --default-reset arst_n --module-name chimera_reg_top --package-name chimera_reg_pkg -P NumClusters=$(NUMCLUSTERS)
+	@sed -i '1i// Copyright 2025 ETH Zurich and University of Bologna.\n// Licensed under the Apache License, Version 2 0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n' $(CHIM_ROOT)/hw/rdl/chimera_reg*.sv
 
 
 # Nonfree components

hw/chimera_top_wrapper.sv

@@ -94,7 +94,9 @@ module chimera_top_wrapper
   localparam type axi_wide_slv_req_t = mem_isl_wide_axi_slv_req_t;
   localparam type axi_wide_slv_rsp_t = mem_isl_wide_axi_slv_rsp_t;
 
-  chimera_reg2hw_t reg2hw;
+  chimera_regs__out_t reg2hw;
+  apb_resp_t apb_reg_soc_rsp;
+  apb_req_t apb_reg_soc_req;
 
   // External AXI crossbar ports
   axi_mst_req_t [iomsb(ChsCfg.AxiExtNumMst):0] axi_mst_req;
@@ -235,7 +237,7 @@ module chimera_top_wrapper
     .reg_rsp_t(reg_rsp_t),
     .apb_req_t(apb_req_t),
     .apb_rsp_t(apb_resp_t)
-  ) i_ext_reg_to_apb (
+  ) i_soc_reg_to_apb (
     .clk_i    (soc_clk_i),
     .rst_ni   (rst_ni),
     .reg_req_i(reg_slv_req[ExtCfgRegsIdx]),
@@ -244,19 +246,35 @@ module chimera_top_wrapper
     .apb_rsp_i(apb_rsp_i)
   );
 
-
   // TOP-LEVEL REG
-
-  chimera_reg_top #(
+  reg_to_apb #(
     .reg_req_t(reg_req_t),
-    .reg_rsp_t(reg_rsp_t)
-  ) i_reg_top (
+    .reg_rsp_t(reg_rsp_t),
+    .apb_req_t(apb_req_t),
+    .apb_rsp_t(apb_resp_t)
+  ) i_ext_reg_to_apb (
     .clk_i    (soc_clk_i),
-    .rst_ni,
+    .rst_ni   (rst_ni),
     .reg_req_i(reg_slv_req[TopLevelCfgRegsIdx]),
     .reg_rsp_o(reg_slv_rsp[TopLevelCfgRegsIdx]),
-    .reg2hw   (reg2hw),
-    .devmode_i('1)
+    .apb_req_o(apb_reg_soc_req),
+    .apb_rsp_i(apb_reg_soc_rsp)
+  );
+
+  chimera_reg_top i_reg_top (
+    .clk          (soc_clk_i),
+    .arst_n       (rst_ni),
+    .s_apb_psel   (apb_reg_soc_req.psel),
+    .s_apb_penable(apb_reg_soc_req.penable),
+    .s_apb_pwrite (apb_reg_soc_req.pwrite),
+    .s_apb_pprot  (apb_reg_soc_req.pprot),
+    .s_apb_paddr  (apb_reg_soc_req.paddr[CHIMERA_REG_TOP_MIN_ADDR_WIDTH-1:0]),
+    .s_apb_pwdata (apb_reg_soc_req.pwdata),
+    .s_apb_pstrb  (apb_reg_soc_req.pstrb),
+    .s_apb_pready (apb_reg_soc_rsp.pready),
+    .s_apb_prdata (apb_reg_soc_rsp.prdata),
+    .s_apb_pslverr(apb_reg_soc_rsp.pslverr),
+    .hwif_out     (reg2hw)
   );
 
 
@@ -306,25 +324,19 @@ module chimera_top_wrapper
   );
 
   logic [ExtClusters-1:0] wide_mem_bypass_mode;
-  assign wide_mem_bypass_mode = {
-    reg2hw.wide_mem_cluster_4_bypass.q,
-    reg2hw.wide_mem_cluster_3_bypass.q,
-    reg2hw.wide_mem_cluster_2_bypass.q,
-    reg2hw.wide_mem_cluster_1_bypass.q,
-    reg2hw.wide_mem_cluster_0_bypass.q
-  };
+  for (
+      genvar extClusterIdx = 0; extClusterIdx < ExtClusters; extClusterIdx++
+  ) begin : gen_wide_mem_bypass
+    assign wide_mem_bypass_mode[extClusterIdx] =
+           reg2hw.wide_mem_cluster_bypass[extClusterIdx].WIDE_MEM_CLUSTER_BYPASS.value;
+  end
 
   logic [ExtClusters-1:0] cluster_clock_gate_en;
   logic [ExtClusters-1:0] clu_clk_gated;
-  assign cluster_clock_gate_en = {
-    reg2hw.cluster_4_clk_gate_en,
-    reg2hw.cluster_3_clk_gate_en,
-    reg2hw.cluster_2_clk_gate_en,
-    reg2hw.cluster_1_clk_gate_en,
-    reg2hw.cluster_0_clk_gate_en
-  };
-
   for (genvar extClusterIdx = 0; extClusterIdx < ExtClusters; extClusterIdx++) begin : gen_clk_gates
+    assign cluster_clock_gate_en[extClusterIdx] =
+           reg2hw.cluster_clk_gate_en[extClusterIdx].CLUSTER_CLK_GATE_EN.value;
+
     tc_clk_gating i_cluster_clk_gate (
       .clk_i    (clu_clk_i),
       .en_i     (~cluster_clock_gate_en[extClusterIdx]),
@@ -335,13 +347,10 @@ module chimera_top_wrapper
 
   logic [ExtClusters-1:0] cluster_rst_n;
   logic [ExtClusters-1:0] cluster_soft_rst_n;
-  assign cluster_soft_rst_n = {
-    ~reg2hw.reset_cluster_4.q,
-    ~reg2hw.reset_cluster_3.q,
-    ~reg2hw.reset_cluster_2.q,
-    ~reg2hw.reset_cluster_1.q,
-    ~reg2hw.reset_cluster_0.q
-  };
+  for (genvar extClusterIdx = 0; extClusterIdx < ExtClusters; extClusterIdx++) begin : gen_soft_rst
+    assign cluster_soft_rst_n[extClusterIdx] =
+           ~reg2hw.reset_cluster[extClusterIdx].RESET_CLUSTER.value;
+  end
 
   // The Rst used for each cluster is the AND gate among all different source of rst in the system that are:
   // - rst_ni: Global asynchronous reset coming from the PAD
@@ -366,7 +375,7 @@ module chimera_top_wrapper
     .clu_clk_i        (clu_clk_gated),
     .rst_ni           (cluster_rst_n),
     .widemem_bypass_i (wide_mem_bypass_mode),
-    .boot_addr_i      (reg2hw.snitch_configurable_boot_addr.q),
+    .boot_addr_i      (reg2hw.snitch_configurable_boot_addr.SNITCH_CONFIGURABLE_BOOT_ADDR.value),
     .debug_req_i      (dbg_ext_req),
     .xeip_i           (xeip_ext),
     .mtip_i           (mtip_ext),

hw/rdl/cheshire_host.rdl

@@ -0,0 +1,21 @@
+// Copyright 2025 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+
+`ifndef __CHESHIRE_HOST_RDL__
+`define __CHESHIRE_HOST_RDL__
+
+`include "chimera_regs.rdl"
+
+addrmap cheshire_host #(
+  longint unsigned NumClusters = 1 // Number of Clusters
+) {
+
+  chimera_regs #(.NumClusters (NumClusters)) chimera_regs @0x1000;
+
+  // TODO: Map the Hyperbus
+  // TODO: Map external reg for chip levelk (FLL, etc...)
+
+};
+
+`endif // __CHESHIRE_HOST_RDL__

hw/rdl/chimera.rdl

@@ -0,0 +1,16 @@
+// Copyright 2025 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+
+`include "cheshire_host.rdl"
+`include "snitch_cluster.rdl"
+
+addrmap chimera_addrmap #(
+  longint unsigned NumClusters = 1 // Number of Clusters
+){
+
+  cheshire_host #(.NumClusters (NumClusters)) host @0x30000000;
+  snitch_cluster snitch_cluster[NumClusters] @0x40000000 += 0x200000;
+  external mem { mementries = 0x40000; memwidth = 8; } l2_mem_island @0x48000000;
+
+};

hw/rdl/chimera_reg_pkg.sv

@@ -0,0 +1,86 @@
+// Copyright 2025 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2 0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
+//  https://github.com/SystemRDL/PeakRDL-regblock
+
+package chimera_reg_pkg;
+
+  localparam CHIMERA_REG_TOP_DATA_WIDTH = 32;
+  localparam CHIMERA_REG_TOP_MIN_ADDR_WIDTH = 7;
+  localparam CHIMERA_REG_TOP_SIZE = 'h70;
+
+  localparam NumClusters = 'h5;
+
+  typedef struct {
+    logic [31:0] value;
+  } chimera_regs_NumClusters_5__snitch_boot_addr__SNITCH_BOOT_ADDR__out_t;
+
+  typedef struct {
+    chimera_regs_NumClusters_5__snitch_boot_addr__SNITCH_BOOT_ADDR__out_t SNITCH_BOOT_ADDR;
+  } chimera_regs_NumClusters_5__snitch_boot_addr__out_t;
+
+  typedef struct {
+    logic [31:0] value;
+  } chimera_regs_NumClusters_5__snitch_configurable_boot_addr__SNITCH_CONFIGURABLE_BOOT_ADDR__out_t;
+
+  typedef struct {
+    chimera_regs_NumClusters_5__snitch_configurable_boot_addr__SNITCH_CONFIGURABLE_BOOT_ADDR__out_t SNITCH_CONFIGURABLE_BOOT_ADDR;
+  } chimera_regs_NumClusters_5__snitch_configurable_boot_addr__out_t;
+
+  typedef struct {
+    logic [31:0] value;
+  } chimera_regs_NumClusters_5__snitch_intr_handler_addr__SNITCH_INTR_HANDLER_ADDR__out_t;
+
+  typedef struct {
+    chimera_regs_NumClusters_5__snitch_intr_handler_addr__SNITCH_INTR_HANDLER_ADDR__out_t SNITCH_INTR_HANDLER_ADDR;
+  } chimera_regs_NumClusters_5__snitch_intr_handler_addr__out_t;
+
+  typedef struct {
+    logic [31:0] value;
+  } chimera_regs_NumClusters_5__snitch_cluster_return__SNITCH_CLUSTER_RETURN__out_t;
+
+  typedef struct {
+    chimera_regs_NumClusters_5__snitch_cluster_return__SNITCH_CLUSTER_RETURN__out_t SNITCH_CLUSTER_RETURN;
+  } chimera_regs_NumClusters_5__snitch_cluster_return__out_t;
+
+  typedef struct {logic value;} chimera_regs_NumClusters_5__reset_cluster__RESET_CLUSTER__out_t;
+
+  typedef struct {
+    chimera_regs_NumClusters_5__reset_cluster__RESET_CLUSTER__out_t RESET_CLUSTER;
+  } chimera_regs_NumClusters_5__reset_cluster__out_t;
+
+  typedef struct {
+    logic value;
+  } chimera_regs_NumClusters_5__cluster_clk_gate_en__CLUSTER_CLK_GATE_EN__out_t;
+
+  typedef struct {
+    chimera_regs_NumClusters_5__cluster_clk_gate_en__CLUSTER_CLK_GATE_EN__out_t CLUSTER_CLK_GATE_EN;
+  } chimera_regs_NumClusters_5__cluster_clk_gate_en__out_t;
+
+  typedef struct {
+    logic value;
+  } chimera_regs_NumClusters_5__wide_mem_cluster_bypass__WIDE_MEM_CLUSTER_BYPASS__out_t;
+
+  typedef struct {
+    chimera_regs_NumClusters_5__wide_mem_cluster_bypass__WIDE_MEM_CLUSTER_BYPASS__out_t WIDE_MEM_CLUSTER_BYPASS;
+  } chimera_regs_NumClusters_5__wide_mem_cluster_bypass__out_t;
+
+  typedef struct {logic value;} chimera_regs_NumClusters_5__cluster_busy__CLUSTER_BUSY__out_t;
+
+  typedef struct {
+    chimera_regs_NumClusters_5__cluster_busy__CLUSTER_BUSY__out_t CLUSTER_BUSY;
+  } chimera_regs_NumClusters_5__cluster_busy__out_t;
+
+  typedef struct {
+    chimera_regs_NumClusters_5__snitch_boot_addr__out_t              snitch_boot_addr;
+    chimera_regs_NumClusters_5__snitch_configurable_boot_addr__out_t snitch_configurable_boot_addr;
+    chimera_regs_NumClusters_5__snitch_intr_handler_addr__out_t      snitch_intr_handler_addr;
+    chimera_regs_NumClusters_5__snitch_cluster_return__out_t         snitch_cluster_return[5];
+    chimera_regs_NumClusters_5__reset_cluster__out_t                 reset_cluster[5];
+    chimera_regs_NumClusters_5__cluster_clk_gate_en__out_t           cluster_clk_gate_en[5];
+    chimera_regs_NumClusters_5__wide_mem_cluster_bypass__out_t       wide_mem_cluster_bypass[5];
+    chimera_regs_NumClusters_5__cluster_busy__out_t                  cluster_busy[5];
+  } chimera_regs__out_t;
+endpackage