Device Tree changes for Purwa #610
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…bug block Add below Coresight devices for APSS debug block: -ETM -TMC ETF -Funnel -Replicator Link: https://lore.kernel.org/all/20251027-cpu_cluster_component_pm-v1-12-31355ac588c2@oss.qualcomm.com/ Signed-off-by: Yuanfang Zhang <[email protected]> Signed-off-by: Jie Gan <[email protected]>
Previously, the eDP panel backlight was enabled via UEFI. Added backlight control node in kernel DTS due to some meta may not enable the backlight. Aligned with other x1e80100-based platforms: the PWM signal is controlled by PMK8550, and the backlight enable signal is handled by PMC8380. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Yongxing Mou <[email protected]>
Embedded Trace Router(ETR) is working as a DDR memory sink to collect tracing data from source device. The CTCU serves as the control unit for the ETR device, managing its behavior to determine how trace data is collected. Link: https://lore.kernel.org/all/20251104-enable-etr-and-ctcu-for-hamoa-v1-2-af552cfb902c@oss.qualcomm.com/ Signed-off-by: Jie Gan <[email protected]>
Enable ST33HTPM TPM over SPI11 on the Hamoa IoT EVK by adding the required SPI and TPM nodes. Link: https://lore.kernel.org/all/20251112-arm64-dts-qcom-hamoa-iot-evk-enable-st33-tpm-on-spi11-v3-1-39b19eb55cc3@oss.qualcomm.com/ Signed-off-by: Khalid Faisal Ansari <[email protected]>
…-SOM platform HAMOA IoT SOM requires PCIe3 and PCIe5 connectivity for SATA controller and SDX65. Add the required sideband signals (PERST#, WAKE#, CLKREQ#), pinctrl states and power supply properties in the device tree, which PCIe3 and PCIe5 require. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Ziyue Zhang <[email protected]> Reviewed-by: Krishna Chaitanya Chundru <[email protected]>
…IOT-EVK board HAMAO IoT EVK uses PCIe5 to connect an SDX65 module for WWAN functionality and PCIe3 to connect a SATA controller. These interfaces require multiple voltage rails: PCIe5 needs 3.3V supplied by vreg_wwan, while PCIe3 requires 12V, 3.3V, and 3.3V AUX rails, controlled via PMIC GPIOs. Add the required fixed regulators with related pin configuration, and connect them to the PCIe3 and PCIe5 ports to ensure proper power for the SDX65 module and SATA controller. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Ziyue Zhang <[email protected]> Reviewed-by: Krishna Chaitanya Chundru <[email protected]>
On X Elite, there is a crypto engine IP block similar to ones found on SM8x50 platforms. Describe the crypto engine and its BAM. Signed-off-by: Harshal Dev <[email protected]> Link: https://lore.kernel.org/lkml/20251127-crypto_dt_node_x1e80100-v3-1-29722003fe83@oss.qualcomm.com/
… for Type-A ports The Multiport controller on Hamoa EVK platform is connected to Two Type-A ports. VBUS for each of these ports are provided by a TPS2559QWDRCTQ1 regulator, controlled from PMIC GPIOs. Add the necessary regulators and GPIO configuration to power these. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Krishna Kurapati <[email protected]> Signed-off-by: Xin Liu <[email protected]>
…t evk board WLAN card is connected to PCIe4 on hamoa iot evk board. Add WLAN node to support power sequence for this WLAN card. Link: https://lore.kernel.org/all/[email protected] Signed-off-by: Yingying Tang <[email protected]>
Document x1e80100 compatible for the True Random Number Generator. Signed-off-by: Harshal Dev <[email protected]> Link: https://lore.kernel.org/lkml/20251124-trng_dt_binding_x1e80100-v1-1-b4eafa0f1077@oss.qualcomm.com/
The x1e80100 SoC has a True Random Number Generator, add the node with the correct compatible set. Signed-off-by: Harshal Dev <[email protected]> Link: https://lore.kernel.org/lkml/20251124-trng_dt_binding_x1e80100-v1-2-b4eafa0f1077@oss.qualcomm.com/
Document the device tree bindings for the PURWA-IOT-EVK board, which uses the Qualcomm X1P42100 SoC. Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Yijie Yang <[email protected]> Link: https://lore.kernel.org/all/[email protected]/
Add the Purwa-IoT-EVK board to the list to enable access to EFI variables. Guarantee that subsystems relying on SCM services can access secure-world features. This change improves reliability and prevents missing functionality or boot-time issues by making service availability explicit. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Yijie Yang <[email protected]> Link: https://lore.kernel.org/all/[email protected]/
The PURWA-IOT-SOM is a compact computing module that integrates a System on Chip (SoC) — specifically the x1p42100 — along with essential components optimized for IoT applications. It is designed to be mounted on carrier boards, enabling the development of complete embedded systems. Make the following peripherals on the SOM enabled: - Regulators on the SOM - Reserved memory regions - PCIe3, PCIe4, PCIe5, PCIe6a - USB0 through USB6 and their PHYs - ADSP, CDSP - Graphic Signed-off-by: Yijie Yang <[email protected]> Link: https://lore.kernel.org/all/[email protected]/
The PURWA-IOT-EVK is an evaluation platform for IoT products, composed of the Purwa IoT SoM and a carrier board. Together, they form a complete embedded system capable of booting to UART. PURWA-IOT-EVK uses the PS8833 as a retimer for USB0, unlike HAMOA-IOT-EVK. Meanwhile, USB0 bypasses the SBU selector FSUSB42. As a result, the glink topology differs from that of HAMOA-IOT-EVK. Make the following peripherals on the carrier board enabled: - UART - On-board regulators - USB Type-C mux - Pinctrl - Embedded USB (EUSB) repeaters - NVMe - pmic-glink - USB DisplayPorts - Bluetooth - WLAN - Audio - PCIe ports for PCIe3 through PCIe6a Signed-off-by: Yijie Yang <[email protected]> Link: https://lore.kernel.org/all/[email protected]/
Purwa will crash if HLOS attempts to access or configure the TPM pins, as these operations require higher privilege levels. Therefore, the TPM pins should be reserved in the DTS until NHLOS provides proper support. Signed-off-by: Yijie Yang <[email protected]>
Add the CAMCC block for x1e80100. The x1e80100 CAMCC block is an iteration of previous CAMCC blocks with the exception of having two required power-domains not just one. Reviewed-by: Vladimir Zapolskiy <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Bryan O'Donoghue <[email protected]> Signed-off-by: Jagadeesh Kona <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected]
…odes on purwa Update the compatible for videocc and camcc nodes to match with their respective purwa(X1P42100) specific drivers. Signed-off-by: Jagadeesh Kona <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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