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Improved GDBServer Support (XML-based register list and support for FPRs) #168

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Improved GDBServer Support (XML-based register list and support for FPRs) #168

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6000b8d
ArchImpl/RV{32,64}IMACFD: re-generate (with floatregfields and fcsr a…
PhilippvK Sep 16, 2025
03e8928
ArchImpl/RV{32,64}IMACFD/RV{32,64}IMACFDArchSpecificImp.cpp: add floa…
PhilippvK Sep 16, 2025
4793904
ArchImpl/RV{32,64}IMACFD: re-generate (expose csrfields to virtualstr…
PhilippvK Sep 16, 2025
7ea0c8a
gdbserver: communicate target features via xml
PhilippvK Sep 16, 2025
1b1df71
RV32IMACFD: add gdbserver xml files
PhilippvK Sep 16, 2025
b4f4b1c
RV64IMACFD: add gdbserver xml files
PhilippvK Sep 16, 2025
8cc4d44
RV{32,64}IMACFD: copy gdbserver xml files to build & install dir
PhilippvK Sep 16, 2025
81253f9
fix xml syntax
PhilippvK Sep 17, 2025
fdfe8ec
RV{32,64}IMACFD: add m2isar-generated virtualstruct fields
PhilippvK Sep 17, 2025
5f22429
RV{32,64}IMACFD: add m2isar-generated gdbcore mapping
PhilippvK Sep 17, 2025
8f5600c
xml fix
PhilippvK Sep 17, 2025
437b9f3
RV{32,64}IMACFD: add m2isar-generated gdbcore mapping
PhilippvK Sep 17, 2025
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15 changes: 14 additions & 1 deletion ArchImpl/RV32IMACFD/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -36,4 +36,17 @@ add_custom_command(
)
INSTALL(FILES "${CMAKE_CURRENT_LIST_DIR}/${PROJECT_NAME}Funcs.h" DESTINATION "include/jit/Arch/${PROJECT_NAME}")

ETISSPluginArch(${PROJECT_NAME})
# handle gdbserver xml files
if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/xml")
add_custom_target(copy_${PROJECT_NAME}_xml ALL
COMMAND ${CMAKE_COMMAND} -E make_directory
"${CMAKE_CURRENT_LIST_DIR}/xml"
COMMAND ${CMAKE_COMMAND} -E copy_directory
"${CMAKE_CURRENT_LIST_DIR}/xml"
"${ETISS_BINARY_DIR}/xml/${PROJECT_NAME}"
)
add_dependencies(${PROJECT_NAME} copy_${PROJECT_NAME}_xml)
install(DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/xml/ DESTINATION xml/${PROJECT_NAME})
endif()

ETISSPluginArch(${PROJECT_NAME})
37 changes: 36 additions & 1 deletion ArchImpl/RV32IMACFD/RV32IMACFD.h
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Expand Up @@ -54,12 +54,47 @@ struct RV32IMACFD {
etiss_uint8 PRIV;
etiss_uint32 DPC;
etiss_uint32 FCSR;
etiss_uint32 FFLAGS;
etiss_uint32 FRM;
etiss_uint32 MSTATUS;
etiss_uint32 MIE;
etiss_uint32 MIP;
etiss_uint32 *CSR[4096];
etiss_uint32 ins_CSR[4096];
etiss_uint64 F[32];
etiss_uint64 FT0;
etiss_uint64 FT1;
etiss_uint64 FT2;
etiss_uint64 FT3;
etiss_uint64 FT4;
etiss_uint64 FT5;
etiss_uint64 FT6;
etiss_uint64 FT7;
etiss_uint64 FS0;
etiss_uint64 FS1;
etiss_uint64 FA0;
etiss_uint64 FA1;
etiss_uint64 FA2;
etiss_uint64 FA3;
etiss_uint64 FA4;
etiss_uint64 FA5;
etiss_uint64 FA6;
etiss_uint64 FA7;
etiss_uint64 FS2;
etiss_uint64 FS3;
etiss_uint64 FS4;
etiss_uint64 FS5;
etiss_uint64 FS6;
etiss_uint64 FS7;
etiss_uint64 FS8;
etiss_uint64 FS9;
etiss_uint64 FS10;
etiss_uint64 FS11;
etiss_uint64 FT8;
etiss_uint64 FT9;
etiss_uint64 FT10;
etiss_uint64 FT11;
etiss_uint64 *F[32];
etiss_uint64 ins_F[32];
etiss_uint32 RES_ADDR;
};

Expand Down
107 changes: 104 additions & 3 deletions ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -79,6 +79,10 @@ void RV32IMACFDArch::resetCPU(ETISS_CPU * cpu,etiss::uint64 * startpointer)
rv32imacfdcpu->ins_CSR[i] = 0;
rv32imacfdcpu->CSR[i] = &rv32imacfdcpu->ins_CSR[i];
}
for (int i = 0; i < 32; ++i) {
rv32imacfdcpu->ins_F[i] = 0;
rv32imacfdcpu->F[i] = &rv32imacfdcpu->ins_F[i];
}

rv32imacfdcpu->ZERO = 0;
rv32imacfdcpu->RA = 0;
Expand Down Expand Up @@ -121,12 +125,43 @@ void RV32IMACFDArch::resetCPU(ETISS_CPU * cpu,etiss::uint64 * startpointer)
rv32imacfdcpu->PRIV = 0;
rv32imacfdcpu->DPC = 0;
rv32imacfdcpu->FCSR = 0;
rv32imacfdcpu->FFLAGS = 0;
rv32imacfdcpu->FRM = 0;
rv32imacfdcpu->MSTATUS = 0;
rv32imacfdcpu->MIE = 0;
rv32imacfdcpu->MIP = 0;
for (int i = 0; i < 32; ++i) {
rv32imacfdcpu->F[i] = 0;
}
rv32imacfdcpu->FT0 = 0;
rv32imacfdcpu->FT1 = 0;
rv32imacfdcpu->FT2 = 0;
rv32imacfdcpu->FT3 = 0;
rv32imacfdcpu->FT4 = 0;
rv32imacfdcpu->FT5 = 0;
rv32imacfdcpu->FT6 = 0;
rv32imacfdcpu->FT7 = 0;
rv32imacfdcpu->FS0 = 0;
rv32imacfdcpu->FS1 = 0;
rv32imacfdcpu->FA0 = 0;
rv32imacfdcpu->FA1 = 0;
rv32imacfdcpu->FA2 = 0;
rv32imacfdcpu->FA3 = 0;
rv32imacfdcpu->FA4 = 0;
rv32imacfdcpu->FA5 = 0;
rv32imacfdcpu->FA6 = 0;
rv32imacfdcpu->FA7 = 0;
rv32imacfdcpu->FS2 = 0;
rv32imacfdcpu->FS3 = 0;
rv32imacfdcpu->FS4 = 0;
rv32imacfdcpu->FS5 = 0;
rv32imacfdcpu->FS6 = 0;
rv32imacfdcpu->FS7 = 0;
rv32imacfdcpu->FS8 = 0;
rv32imacfdcpu->FS9 = 0;
rv32imacfdcpu->FS10 = 0;
rv32imacfdcpu->FS11 = 0;
rv32imacfdcpu->FT8 = 0;
rv32imacfdcpu->FT9 = 0;
rv32imacfdcpu->FT10 = 0;
rv32imacfdcpu->FT11 = 0;
rv32imacfdcpu->RES_ADDR = 0;

rv32imacfdcpu->X[0] = &rv32imacfdcpu->ZERO;
Expand Down Expand Up @@ -162,9 +197,43 @@ void RV32IMACFDArch::resetCPU(ETISS_CPU * cpu,etiss::uint64 * startpointer)
rv32imacfdcpu->X[30] = &rv32imacfdcpu->T5;
rv32imacfdcpu->X[31] = &rv32imacfdcpu->T6;
rv32imacfdcpu->CSR[3] = &rv32imacfdcpu->FCSR;
rv32imacfdcpu->CSR[1] = &rv32imacfdcpu->FFLAGS;
rv32imacfdcpu->CSR[2] = &rv32imacfdcpu->FRM;
rv32imacfdcpu->CSR[768] = &rv32imacfdcpu->MSTATUS;
rv32imacfdcpu->CSR[772] = &rv32imacfdcpu->MIE;
rv32imacfdcpu->CSR[836] = &rv32imacfdcpu->MIP;
rv32imacfdcpu->F[0] = &rv32imacfdcpu->FT0;
rv32imacfdcpu->F[1] = &rv32imacfdcpu->FT1;
rv32imacfdcpu->F[2] = &rv32imacfdcpu->FT2;
rv32imacfdcpu->F[3] = &rv32imacfdcpu->FT3;
rv32imacfdcpu->F[4] = &rv32imacfdcpu->FT4;
rv32imacfdcpu->F[5] = &rv32imacfdcpu->FT5;
rv32imacfdcpu->F[6] = &rv32imacfdcpu->FT6;
rv32imacfdcpu->F[7] = &rv32imacfdcpu->FT7;
rv32imacfdcpu->F[8] = &rv32imacfdcpu->FS0;
rv32imacfdcpu->F[9] = &rv32imacfdcpu->FS1;
rv32imacfdcpu->F[10] = &rv32imacfdcpu->FA0;
rv32imacfdcpu->F[11] = &rv32imacfdcpu->FA1;
rv32imacfdcpu->F[12] = &rv32imacfdcpu->FA2;
rv32imacfdcpu->F[13] = &rv32imacfdcpu->FA3;
rv32imacfdcpu->F[14] = &rv32imacfdcpu->FA4;
rv32imacfdcpu->F[15] = &rv32imacfdcpu->FA5;
rv32imacfdcpu->F[16] = &rv32imacfdcpu->FA6;
rv32imacfdcpu->F[17] = &rv32imacfdcpu->FA7;
rv32imacfdcpu->F[18] = &rv32imacfdcpu->FS2;
rv32imacfdcpu->F[19] = &rv32imacfdcpu->FS3;
rv32imacfdcpu->F[20] = &rv32imacfdcpu->FS4;
rv32imacfdcpu->F[21] = &rv32imacfdcpu->FS5;
rv32imacfdcpu->F[22] = &rv32imacfdcpu->FS6;
rv32imacfdcpu->F[23] = &rv32imacfdcpu->FS7;
rv32imacfdcpu->F[24] = &rv32imacfdcpu->FS8;
rv32imacfdcpu->F[25] = &rv32imacfdcpu->FS9;
rv32imacfdcpu->F[26] = &rv32imacfdcpu->FS10;
rv32imacfdcpu->F[27] = &rv32imacfdcpu->FS11;
rv32imacfdcpu->F[28] = &rv32imacfdcpu->FT8;
rv32imacfdcpu->F[29] = &rv32imacfdcpu->FT9;
rv32imacfdcpu->F[30] = &rv32imacfdcpu->FT10;
rv32imacfdcpu->F[31] = &rv32imacfdcpu->FT11;

rv32imacfdcpu->PRIV = 3ULL;
rv32imacfdcpu->DPC = 0LL;
Expand Down Expand Up @@ -257,6 +326,38 @@ const char * const reg_name[] =
"X29",
"X30",
"X31",
"F0",
"F1",
"F2",
"F3",
"F4",
"F5",
"F6",
"F7",
"F8",
"F9",
"F10",
"F11",
"F12",
"F13",
"F14",
"F15",
"F16",
"F17",
"F18",
"F19",
"F20",
"F21",
"F22",
"F23",
"F24",
"F25",
"F26",
"F27",
"F28",
"F29",
"F30",
"F31",
};

etiss::instr::InstructionGroup ISA16_RV32IMACFD("ISA16_RV32IMACFD", 16);
Expand Down
15 changes: 12 additions & 3 deletions ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -322,11 +322,20 @@ std::shared_ptr<etiss::VirtualStruct> RV32IMACFDArch::getVirtualStruct(ETISS_CPU
}
);

for (uint32_t i = 0; i < 32; ++i){
ret->addField(new RegField_RV32IMACFD(*ret,i));
for (uint32_t i = 0; i < 32; i += 1){
ret->addField(new RegField_RV32IMACFD(*ret, i));
}

for (uint32_t i = 0; i < 32; i += 1){
ret->addField(new FloatRegField_RV32IMACFD(*ret, i));
}
for (uint32_t i = 1; i < 4; i += 1){
ret->addField(new CSRField_RV32IMACFD(*ret, i));
}
ret->addField(new CSRField_RV32IMACFD(*ret, 768));
ret->addField(new CSRField_RV32IMACFD(*ret, 772));
ret->addField(new CSRField_RV32IMACFD(*ret, 836));
ret->addField(new pcField_RV32IMACFD(*ret));

return ret;
}

Expand Down
77 changes: 77 additions & 0 deletions ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h
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Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,8 @@
#ifndef ETISS_RV32IMACFDArch_RV32IMACFDARCHSPECIFICIMP_H_
#define ETISS_RV32IMACFDArch_RV32IMACFDARCHSPECIFICIMP_H_

#include "RV32IMACFDFuncs.h"

/**
@brief VirtualStruct for RV32IMACFD architecture to faciliate register acess

Expand Down Expand Up @@ -55,6 +57,81 @@ class RegField_RV32IMACFD : public etiss::VirtualStruct::Field{
}
};

class FloatRegField_RV32IMACFD : public etiss::VirtualStruct::Field{
private:
const unsigned gprid_;
public:
FloatRegField_RV32IMACFD(etiss::VirtualStruct & parent,unsigned gprid)
: Field(parent,
std::string("F")+etiss::toString(gprid),
std::string("F")+etiss::toString(gprid),
R|W,
8
),
gprid_(gprid)
{}

FloatRegField_RV32IMACFD(etiss::VirtualStruct & parent, std::string name, unsigned gprid)
: Field(parent,
name,
name,
R|W,
8
),
gprid_(gprid)
{}

virtual ~FloatRegField_RV32IMACFD(){}

protected:
virtual uint64_t _read() const {
return (uint64_t) *((RV32IMACFD*)parent_.structure_)->F[gprid_];
}

virtual void _write(uint64_t val) {
etiss::log(etiss::VERBOSE, "write to ETISS cpu state", name_, val);
*((RV32IMACFD*)parent_.structure_)->F[gprid_] = (etiss_uint64) val;
}
};


class CSRField_RV32IMACFD : public etiss::VirtualStruct::Field{
private:
const unsigned gprid_;
public:
CSRField_RV32IMACFD(etiss::VirtualStruct & parent,unsigned gprid)
: Field(parent,
std::string("CSR")+etiss::toString(gprid),
std::string("CSR")+etiss::toString(gprid),
R|W,
8
),
gprid_(gprid)
{}

CSRField_RV32IMACFD(etiss::VirtualStruct & parent, std::string name, unsigned gprid)
: Field(parent,
name,
name,
R|W,
8
),
gprid_(gprid)
{}

virtual ~CSRField_RV32IMACFD(){}

protected:
virtual uint64_t _read() const {
return (uint64_t) RV32IMACFD_csr_read((ETISS_CPU*)parent_.structure_, nullptr, nullptr, (etiss_uint64) gprid_);
}

virtual void _write(uint64_t val) {
etiss::log(etiss::VERBOSE, "write to ETISS cpu state", name_, val);
RV32IMACFD_csr_write((ETISS_CPU*)parent_.structure_, nullptr, nullptr, gprid_, (etiss_uint64) val);
}
};


class pcField_RV32IMACFD : public etiss::VirtualStruct::Field{
public:
Expand Down
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