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4 changes: 2 additions & 2 deletions docs/microarchitecture.md
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Expand Up @@ -9,7 +9,7 @@ Vortex uses the SIMT (Single Instruction, Multiple Threads) execution model with
- Each thread has its own register file (32 int + 32 fp registers)
- Threads execute in parallel
- **Warps**
- A logical clster of threads
- A logical cluster of threads
- Each thread in a warp execute the same instruction
- The PC is shared; maintain thread mask for Writeback
- Warp's execution is time-multiplexed at log steps
Expand Down Expand Up @@ -80,4 +80,4 @@ Vortex has a 6-stage pipeline:
- Grouping of sockets sharing L2 cache

### Vortex Cache Subsystem
More details about the cache subsystem are provided [here](./cache_subsystem.md).
More details about the cache subsystem are provided [here](./cache_subsystem.md).