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Add look ahead interface for working COMPRESSED_ISA #65

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c1b65b5
Add look ahead interface for working COMPRESSED
tomtor Jan 28, 2019
a585e0d
Speed up with 1 cycle
tomtor Jan 29, 2019
7cc51a5
Stall on access outside defined memory regions
tomtor Jan 29, 2019
a5179e2
Fix register storage for QREG option
tomtor Jan 30, 2019
8bc1716
Fix Diamond BRAM inference by merging always blocks
tomtor Feb 2, 2019
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11 changes: 6 additions & 5 deletions examples/soc_ecp5_evn/Makefile
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Original file line number Diff line number Diff line change
@@ -1,14 +1,15 @@
firmware.elf: sections.lds start.s firmware.c
riscv32-unknown-elf-gcc -march=rv32i -Wl,-Bstatic,-T,sections.lds,--strip-debug -ffreestanding -nostdlib -o firmware.elf start.s firmware.c
firmware.elf: sections.lds start.S firmware.c printf.c
riscv32-unknown-elf-gcc -march=rv32imc -Os -mabi=ilp32 -Wl,-Bstatic,-T,sections.lds,--strip-debug -ffreestanding -nostdlib -o firmware.elf start.S firmware.c -DPRINTF_DISABLE_SUPPORT_LONG_LONG -DPRINTF_DISABLE_SUPPORT_PTRDIFF_T printf.c -lm -lc -lgcc
#/opt/riscv32imc/bin/riscv32-unknown-elf-gcc -march=rv32imc -Os -mabi=ilp32 -Wl,-Bstatic,-T,sections.lds,--strip-debug -ffreestanding -nostdlib -o firmware.elf start.S firmware.c -DPRINTF_DISABLE_SUPPORT_LONG_LONG -DPRINTF_DISABLE_SUPPORT_PTRDIFF_T printf.c -lm -lc -lgcc

firmware.bin: firmware.elf
riscv32-unknown-elf-objcopy -O binary firmware.elf /dev/stdout > firmware.bin

firmware.hex: firmware.bin
python3 makehex.py $^ 4096 > $@
python3 makehex.py $^ 16384 > $@

attosoc_tb.vvp: attosoc_tb.v attosoc.v picorv32.v simpleuart.v
iverilog -s testbench -o $@ $^
attosoc_tb.vvp: attosoc_tb.v attosoc.v picorv32.v simpleuart.v firmware.hex
iverilog -s testbench -o $@ attosoc_tb.v attosoc.v picorv32.v simpleuart.v

attosoc_sim: attosoc_tb.vvp firmware.hex
vvp -N $<
Expand Down
46 changes: 25 additions & 21 deletions examples/soc_ecp5_evn/attosoc.v
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Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,7 @@ module attosoc (
input clk,
output reg [7:0] led,
output uart_tx,
input uart_rx,
input uart_rx
);

reg [5:0] reset_cnt = 0;
Expand All @@ -38,14 +38,17 @@ module attosoc (
reset_cnt <= reset_cnt + !resetn;
end

parameter integer MEM_WORDS = 8192;
// parameter integer MEM_WORDS = 8192;
parameter integer MEM_WORDS = 16384;
parameter [31:0] STACKADDR = 32'h 0000_0000 + (4*MEM_WORDS); // end of memory
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000; // start of memory

reg [31:0] ram [0:MEM_WORDS-1];
initial $readmemh("firmware.hex", ram);
reg [31:0] ram_rdata;
reg ram_ready;

reg [31:0] irq = 32'h 0000_0000;
wire [31:0] eoi;

wire mem_valid;
wire mem_instr;
Expand All @@ -54,18 +57,16 @@ module attosoc (
wire [31:0] mem_wdata;
wire [3:0] mem_wstrb;
wire [31:0] mem_rdata;
wire [31:0] mem_la_addr;

always @(posedge clk)
begin
ram_ready <= 1'b0;
ram_rdata <= ram[mem_la_addr[23:2]];
if (mem_addr[31:24] == 8'h00 && mem_valid) begin
if (mem_wstrb[0]) ram[mem_addr[23:2]][7:0] <= mem_wdata[7:0];
if (mem_wstrb[1]) ram[mem_addr[23:2]][15:8] <= mem_wdata[15:8];
if (mem_wstrb[2]) ram[mem_addr[23:2]][23:16] <= mem_wdata[23:16];
if (mem_wstrb[3]) ram[mem_addr[23:2]][31:24] <= mem_wdata[31:24];

ram_rdata <= ram[mem_addr[23:2]];
ram_ready <= 1'b1;
end
end

Expand Down Expand Up @@ -98,22 +99,22 @@ module attosoc (


assign mem_ready = (iomem_valid && iomem_ready) ||
simpleuart_reg_div_sel || (simpleuart_reg_dat_sel && !simpleuart_reg_dat_wait) ||
ram_ready;
simpleuart_reg_div_sel || (simpleuart_reg_dat_sel && !simpleuart_reg_dat_wait)
|| mem_addr < STACKADDR;

assign mem_rdata = simpleuart_reg_div_sel ? simpleuart_reg_div_do :
simpleuart_reg_dat_sel ? simpleuart_reg_dat_do :
ram_rdata;
picorv32 #(
.STACKADDR(STACKADDR),
.PROGADDR_RESET(PROGADDR_RESET),
.PROGADDR_IRQ(32'h 0000_0000),
.BARREL_SHIFTER(0),
.COMPRESSED_ISA(0),
.ENABLE_MUL(0),
.ENABLE_DIV(0),
.ENABLE_IRQ(0),
.ENABLE_IRQ_QREGS(0)
.PROGADDR_IRQ(32'h 0000_0010),
.BARREL_SHIFTER(1),
.COMPRESSED_ISA(1),
.ENABLE_MUL(1),
.ENABLE_DIV(1),
.ENABLE_IRQ(1),
.ENABLE_IRQ_QREGS(1)
) cpu (
.clk (clk ),
.resetn (resetn ),
Expand All @@ -123,7 +124,10 @@ module attosoc (
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata )
.mem_rdata (mem_rdata ),
.irq (irq ),
.eoi (eoi ),
.mem_la_addr (mem_la_addr)
);

simpleuart simpleuart (
Expand Down Expand Up @@ -158,11 +162,11 @@ module picosoc_regs (
output [31:0] rdata1,
output [31:0] rdata2
);
reg [31:0] regs [0:31];
reg [31:0] regs [0:35]; // 32 + 4 QREGS

always @(posedge clk)
if (wen) regs[waddr[4:0]] <= wdata;
if (wen) regs[waddr] <= wdata;

assign rdata1 = regs[raddr1[4:0]];
assign rdata2 = regs[raddr2[4:0]];
assign rdata1 = regs[raddr1];
assign rdata2 = regs[raddr2];
endmodule
8 changes: 4 additions & 4 deletions examples/soc_ecp5_evn/attosoc_tb.v
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Original file line number Diff line number Diff line change
Expand Up @@ -5,10 +5,10 @@ module testbench();
always #5 clk = (clk === 1'b0);

initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);

repeat (10) begin
repeat (4) begin
repeat (50000) @(posedge clk);
$display("+50000 cycles");
end
Expand All @@ -18,7 +18,7 @@ module testbench();
wire [7:0] led;

always @(led) begin
#1 $display("%b", led);
#1 $display("LED: %b", led);
end

attosoc uut (
Expand Down
3 changes: 2 additions & 1 deletion examples/soc_ecp5_evn/ecp5evn.lpf
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Expand Up @@ -19,7 +19,8 @@ IOBUF PORT "led[5]" IO_TYPE=LVCMOS25;
IOBUF PORT "led[6]" IO_TYPE=LVCMOS25;
IOBUF PORT "led[7]" IO_TYPE=LVCMOS25;

LOCATE COMP "uart_tx" SITE "P3";
# LOCATE COMP "uart_tx" SITE "P3";
LOCATE COMP "uart_tx" SITE "L19";
LOCATE COMP "uart_rx" SITE "P2";

IOBUF PORT "uart_tx" IO_TYPE=LVCMOS33;
Expand Down
31 changes: 24 additions & 7 deletions examples/soc_ecp5_evn/firmware.c
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Original file line number Diff line number Diff line change
@@ -1,21 +1,32 @@
#include <stdint.h>
#include <stdlib.h>
#include <math.h>

#include "printf.h"

#define LED (*(volatile uint32_t*)0x02000000)

#define reg_uart_clkdiv (*(volatile uint32_t*)0x02000004)
#define reg_uart_data (*(volatile uint32_t*)0x02000008)

void putchar(char c)
void _putchar(char c)
{
if (c == '\n')
putchar('\r');
_putchar('\r');
reg_uart_data = c;
}

#define uartchar _putchar

void print(const char *p)
{
while (*p)
putchar(*(p++));
uartchar(*(p++));
}

void trap()
{
print("TRAP\r\n");
}

void delay() {
Expand All @@ -25,11 +36,17 @@ void delay() {

int main() {
reg_uart_clkdiv = 416;
int count = 0;
while (1) {
LED = 0xFF;
print("hello world\n");
delay();
LED = 0x00;
LED = ++count;
#if 0
asm("ebreak");
*((int*)0x0000700f) = 1;
#endif
//print("hello world\n");
//printf("hello world %d\n", count);
printf("hello printf: %d %f\n", count, sqrt(count));

delay();
}
}
6 changes: 4 additions & 2 deletions examples/soc_ecp5_evn/picorv32.v
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Expand Up @@ -22,7 +22,7 @@
// `define DEBUGNETS
// `define DEBUGREGS
// `define DEBUGASM
// `define DEBUG
`define DEBUG

`ifdef DEBUG
`define debug(debug_command) debug_command
Expand Down Expand Up @@ -122,6 +122,7 @@ module picorv32 #(
output reg rvfi_trap,
output reg rvfi_halt,
output reg rvfi_intr,
output reg [ 1:0] rvfi_mode,
output reg [ 4:0] rvfi_rs1_addr,
output reg [ 4:0] rvfi_rs2_addr,
output reg [31:0] rvfi_rs1_rdata,
Expand Down Expand Up @@ -1533,7 +1534,7 @@ module picorv32 #(
do_waitirq <= 1;
end else
if (decoder_trigger) begin
`debug($display("-- %-0t", $time);)
`debug($display("-- %-0t pending:%b", $time, irq_pending);)
irq_delay <= irq_active;
reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
if (ENABLE_TRACE)
Expand Down Expand Up @@ -1962,6 +1963,7 @@ module picorv32 #(
rvfi_trap <= trap;
rvfi_halt <= trap;
rvfi_intr <= dbg_irq_enter;
rvfi_mode <= 3;

if (!resetn) begin
dbg_irq_call <= 0;
Expand Down
2 changes: 1 addition & 1 deletion examples/soc_ecp5_evn/pll.v
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Expand Up @@ -24,6 +24,6 @@ module pll_12_50(input clki, output clko);
.PHASEDIR(1'b0),
.PHASESTEP(1'b0),
.PLLWAKESYNC(1'b0),
.ENCLKOP(1'b0),
.ENCLKOP(1'b0)
);
endmodule
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